24LC08
8K-Bit Serial EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The 24LC08 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of
a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to
V CC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to two 24LC08 devices can be
connected to the same I2C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter
or receiver, but the master device determines which bus operating mode would be active.
VCC
VCC
R
R
SDA
SCL
Slave 1
24LC08
Slave 2
24LC08
Bus Master
(Transmitter/
Receiver)
Tx/Rx
A0 A1 A2
Tx/Rx
A0 A1 A2
MCU
To VCC or VSS
To VCC or VSS
NOTES:
1. The A0, A1 do not affect the device address of the 24LC08.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
* All specs and applications shown above subject to change without prior notice.
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Rev 1.1 Nov.18, 2002
Page 5 of 23
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