CAT1021, CAT1022, CAT1023
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
pF
(1)
COUT
Output Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6
pF
AC CHARACTERISTICS
CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
V
Memory Read & Write Cycle(2)
Symbol Parameter
Min
Max
400
100
Units
kHz
ns
fSCL
tSP
tLOW
tHIGH
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
1.3
0.6
µs
Clock High Period
µs
(1)
tR
SDA and SCL Rise Time
300
300
ns
(1)
tF
SDA and SCL Fall Time
ns
tHD; STA
tSU; STA
tHD; DAT
tSU; DAT
tSU; STO
tAA
Start Condition Hold Time
0.6
0.6
0
µs
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
µs
ns
Data Input Setup Time
100
0.6
ns
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
µs
900
5
ns
tDH
50
ns
(1)
tBUF
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
µs
(3)
tWC
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-3009 Rev. M
CATALYST [ CATALYST SEMICONDUCTOR ]
