CAT1021, CAT1022, CAT1023
DEVICE OPERATION
Reset Controller Description
TheCAT1021/22/23precisionRESETcontrollersensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM are
aborted and no new communications are allowed. In this
condition aninternal write cycleto thememory cannot be
started, but an in progress internal non-volatile memory
write cycle can not be aborted. An internal write cycle
initiated before the Reset condition can be successfully
finishedifthereisenoughtime(5ms)beforeVCCreaches
the minimum value of 2V.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point
the reset outputs will be pulled up or down by their
respective pull up/down resistors.
In addition, the CAT1021 includes a Write Protection Input
which when tied to VCC will disable any write operations
to the device.
During power-down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designedtoignorethefastnegativegoingVCC transient
pulses (glitches).
Watchdog Timer
TheWatchdogTimerprovidesanindependentprotection
for microcontrollers. During a system failure, CAT1021/
22/23 devices will provide a reset signal after a time-out
intervalof1.6secondsforalackofactivity. TheCAT1023
is designed with the Watchdog timer feature on the WDI
pin. The CAT1021 and CAT1022 monitor the SDA line. If
WDI or SDA does not toggle within a 1.6 second interval,
theresetconditionwillbegeneratedontheresetoutputs.
The watchdog timer is cleared by any transition on a
monitored line.
Reset output timing is shown in Figure 1.
Manual Reset Operation
TheRESET pincanoperateasresetoutputandmanual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msectimerwillbegintotimetheresetinterval. Ifexternal
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
As long as reset signal is asserted, the watchdog timer
will not count and will stay cleared.
TheCAT1021/22/23alsohaveaseparatemanualreset
input. Driving the MR input low by connecting a
pushbutton (normally open) from MR pin to GND will
generatearesetcondition.Theinputhasaninternalpull
up resistor.
Reset remains asserted while MR is low and for the
Reset Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not
generate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR input is
shown in Figure 2.
Hardware Data Protection
The CAT1021/22/23 supervisors have been designed
to solve many of the data corruption issues that have
long been associated with serial EEPROMs. Data
corruption occurs when incorrect data is stored in a
memory location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the
Doc No. 3009, Rev. K
7
CATALYST [ CATALYST SEMICONDUCTOR ]
