93C46/56/57/66/86
A.C. CHARACTERISTICS (93C46/56/57/66)
Limits
VCC
2.5V-6V
VCC
1.8V-6V*
=
=
VCC
4.5V-5.5V
=
Test
SYMBOL PARAMETER
Min.
200
0
Max.
Min.
Max.
Min.
50
Max. UNITS Conditions
ns
tCSS
tCSH
tDIS
CS Setup Time
100
0
CS Hold Time
0
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
VIL = 0.45V
VIH = 2.4V
CL = 100pF
VOL = 0.8V
DI Setup Time
400
400
200
200
100
100
tDIH
tPD1
tPD0
DI Hold Time
Output Delay to 1
1
1
0.5
0.5
200
10
0.25
0.25
100
10
Output Delay to 0
VOH = 2.0v
CL = 100pF
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
10
tEW
tCSMIN
tSKHI
tSKLOW
tSV
1
1
1
0.5
0.5
0.5
0.25
0.25
0.25
1
0.5
0.25
CL = 100pF
SKMAX
DC
250
DC
500
DC
1000 KHZ
* Preliminary data for 93C56/57/66
A.C. CHARACTERISTICS (93C86)
Limits
VCC
2.5V-6V
VCC
1.8V-6V*
=
=
VCC
4.5V-5.5V
=
Test
SYMBOL PARAMETER
Min.
200
0
Max.
Min.
Max.
Min.
50
0
Max. UNITS Conditions
ns
tCSS
tCSH
tDIS
CS Setup Time
150
0
CS Hold Time
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
VIL = 0.45V
VIH = 2.4V
CL = 100pF
VOL = 0.8V
DI Setup Time
400
400
250
250
50
50
tDIH
tPD1
tPD0
DI Hold Time
Output Delay to 1
1
1
0.5
0.5
200
5
0.1
0.1
100
5
Output Delay to 0
VOH = 2.0v
CL = 100pF
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
5
tEW
tCSMIN
tSKHI
tSKLOW
tSV
1
1
1
0.5
0.5
0.5
0.1
0.1
0.1
1
0.5
0.1
CL = 100pF
SKMAX
DC
250
DC
1000
DC
3000 KHZ
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25056-00 2/98 M-1
4
CATALYST [ CATALYST SEMICONDUCTOR ]
