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25C128 参数 Datasheet PDF下载

25C128图片预览
型号: 25C128
PDF下载: 下载PDF文件 查看货源
内容描述: 128K / 256K位SPI串行E2PROM CMOS [128K/256K-Bit SPI Serial CMOS E2PROM]
分类和应用: 可编程只读存储器
文件页数/大小: 11 页 / 63 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT25C128/256  
to protect quarter of the memory, half of the memory or  
the entire memory by setting these bits. Once protected  
the user may only read from the protected portion of the  
array. These bits are non-volatile.  
STATUS REGISTER  
The Status Register indicates the status of the device.  
TheRDY(Ready)bitindicateswhethertheCAT25C128/  
256 is busy with a write operation. When set to 1 a write  
cycle is in progress and when set to 0 the device  
indicates it is ready. This bit is read only  
TheWPEN(WriteProtectEnable)isanenablebitforthe  
WP pin. The WPpin and WPEN bit in the status register  
control the programmable hardware write protect fea-  
ture. Hardware write protection is enabled when WP is  
low and WPEN bit is set to high. The user cannot write  
tothestatusregister(includingtheblockprotectbitsand  
the WPEN bit) and the block protected sections in the  
memory array when the chip is hardware write pro-  
tected. Only the sections of the memory array that are  
not block protected can be written. Hardware write  
protection is disabled when either WP pin is high or the  
WPEN bit is zero.  
The WEL (Write Enable) bit indicates the status of the  
writeenablelatch. Whensetto1, thedeviceisinaWrite  
Enable state and when set to 0 the device is in a Write  
Disablestate. TheWELbit canonlybesetbytheWREN  
instruction and can be reset by the WRDI instruction.  
The BPO and BP1 (Block Protect) bits indicate which  
blocks are currently protected. These bits are set by the  
user issuing the WRSR instruction. The user is allowed  
STATUS REGISTER  
7
6
5
4
3
2
1
0
WPEN  
X
X
X
BP1  
BP0  
WEL  
RDY  
BLOCK PROTECTION BITS  
Status Register Bits  
Array Address  
Protected  
Protection  
BP1  
BPO  
25C128  
25C256  
None  
0
0
1
1
0
1
0
1
None  
No Protection  
3000-3FFF  
2000-3FFF  
0000-3FFF  
6000-7FFF  
4000-7FFF  
0000-7FFF  
Quarter Array Protection  
Half Array Protection  
Full Array Protection  
WRITE PROTECT ENABLE OPERATION  
Protected  
Blocks  
Unprotected  
Blocks  
Status  
WPEN  
WP  
X
WEL  
Register  
0
0
1
1
X
X
0
1
0
1
0
1
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
Writable  
Protected  
Writable  
Protected  
Writable  
Protected  
Writable  
X
Low  
Low  
High  
High  
Protected  
Protected  
Protected  
Writable  
Doc. No. 25088-00 1/01  
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