BSI
BS616LV1615
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns CYCLE TIME : 55ns
PARAMETER
DESCRIPTION
Read Cycle Time
Vcc = 4.5~5.5V
Vcc = 4.5~5.5V
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tRC
70
--
--
--
--
--
10
5
--
--
--
--
--
--
--
--
--
--
--
--
--
55
--
--
--
--
--
10
5
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tELQV
tBA
tAA
Address Access Time
70
70
70
35
35
--
55
55
55
30
30
--
tACS1
tACS2
(CE1)
(CE2)
Chip Select Access Time
Chip Select Access Time
(1)
tBA
(LB,UB)
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
tGLQV
tELQX
tBE
tOE
tCLZ
tBE
(CE2,CE1)
(LB,UB)
--
--
tGLQX
tEHQZ
tBDO
tGHQZ
tOLZ
tCHZ
tBDO
tOHZ
5
--
5
--
(CE2,CE1)
--
--
--
35
35
30
--
--
--
30
30
25
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
t
t
AXOX
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
Revision 2.1
Jan. 2004
R0201-BS616LV1615
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
