BSI
BS616LV4010
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Vcc/0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
AC TEST LOADS AND WAVEFORMS
Ω
Ω
1269
1269
5PF
3.3V
3.3V
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
OUTPUT
OUTPUT
,
100PF
DON T CARE:
CHANGE :
STATE
UNKNOWN
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
ANY CHANGE
PERMITTED
Ω
Ω
1404
1404
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
MIN. TYP. MAX.
CYCLE TIME : 100ns
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
tAVAX
tAVQV
tELQV
tBA
tRC
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACS
Chip Select Access Time
(CE)
--
--
(1)
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
--
--
tGLQV
tELQX
tBE
tOE
--
--
tCLZ
tBE
(CE)
10
10
10
--
15
15
15
--
(LB,UB)
--
--
tGLQX
tEHQZ
tBDO
tGHQZ
tOLZ
tCHZ
tBDO
tOHZ
--
--
(CE)
35
35
30
40
40
35
(LB,UB)
--
--
--
--
tAXOX
tOH
Data Hold from Address Change
10
--
--
15
--
--
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
Revision 2.4
Jan. 2004
R0201-BS616LV4010
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
