BSI
BS616LV1012
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
Vcc
CE
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
READ CYCLE
JEDEC
PARAMETER
CYCLE TIME : 70ns
CYCLE TIME : 55ns
(Vcc = 2.8~3.6V)
PARAMETER
(Vcc = 2.5~3.6V)
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
t
t
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
25
25
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
--
--
ELQV
ACS
(1)
t
t
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
(LB,UB)
(LB,UB)
--
--
BA
BA
t
t
--
--
GLQV
OE
t
t
10
10
5
10
10
5
E1LQX
CLZ
t
t
--
--
BE
BE
t
t
--
--
GLQX
OLZ
t
t
--
20
20
20
--
25
25
25
EHQZ
CHZ
t
t
--
--
BDO
BDO
t
t
--
--
GHQZ
OHZ
t
t
Data Hold from Address Change
AXOX
OH
10
--
--
10
--
--
ns
NOTE :
1. tBA is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
Revision 1.0
Apr. 2004
R0201-BS616LV1012
4
BSI [ BRILLIANCE SEMICONDUCTOR ]
