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BS616LV1010EI70 参数 Datasheet PDF下载

BS616LV1010EI70图片预览
型号: BS616LV1010EI70
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗CMOS SRAM 64K ×16位 [Very Low Power CMOS SRAM 64K X 16 bit]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 11 页 / 209 K
品牌: BSI [ BRILLIANCE SEMICONDUCTOR ]
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BS616LV1010  
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)  
SYMBOL  
VDR  
PARAMETER  
VCC for Data Retention  
Data Retention Current  
TEST CONDITIONS  
CEVCC-0.2V  
MIN.  
1.5  
--  
TYP. (1)  
MAX.  
UNITS  
--  
0.02  
--  
--  
0.5  
--  
V
VINVCC-0.2V or VIN0.2V  
CEVCC-0.2V  
(3)  
ICCDR  
uA  
ns  
ns  
VINVCC-0.2V or VIN0.2V  
Chip Deselect to Data  
Retention Time  
tCDR  
0
See Retention Waveform  
(2)  
tR  
Operation Recovery Time  
tRC  
--  
--  
1. VCC=1.5V, TA=25OC and not 100% tested.  
2. tRC = Read Cycle Time.  
3. ICCDR(Max.) is 0.3uA at TA=70OC.  
n LOW VCC DATA RETENTION WAVEFORM (CE Controlled)  
Data Retention Mode  
DR1.5V  
V
VCC  
VCC  
VCC  
CE  
tCDR  
tR  
CEVCC - 0.2V  
VIH  
VIH  
n AC TEST CONDITIONS  
n KEY TO SWITCHING WAVEFORMS  
(Test Load and Input/Output Reference)  
WAVEFORM  
INPUTS  
OUTPUTS  
Input Pulse Levels  
Vcc / 0V  
1V/ns  
MUST BE  
STEADY  
MUST BE  
STEADY  
Input Rise and Fall Times  
Input and Output Timing  
Reference Level  
0.5Vcc  
MAY CHANGE  
WILL BE CHANGE  
FROM HTO L”  
FROM HTO L”  
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ  
CL = 5pF+1TTL  
CL = 30pF+1TTL  
Output Load  
Others  
MAY CHANGE  
WILL BE CHANGE  
FROM LTO H”  
FROM LTO H”  
ALL INPUT PULSES  
DONT CARE  
ANY CHANGE  
PERMITTED  
CHANGE :  
STATE UNKNOW  
VCC  
1 TTL  
90%  
90%  
Output  
10%  
10%  
GND  
CENTER LINE IS  
HIGH INPEDANCE  
OFFSTATE  
(1)  
®
¬
®
¬
DOES NOT  
APPLY  
CL  
Rise Time:  
1V/ns  
Fall Time:  
1V/ns  
1. Including jig and scope capacitance.  
Revision 2.6  
R0201-BS616LV1010  
4
May.  
2006