BH62UV1601
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
MUST BE
STEADY
MUST BE
STEADY
Input and Output Timing
Reference Level
0.5Vcc
tCLZ1, tCLZ2, tOLZ, tCHZ1
tCHZ2, tOHZ, tWHZ, tOW
,
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
(1)
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
®
¬
®
¬
CL
DOES NOT
APPLY
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns
PARANETER
DESCRIPTION
Read Cycle Time
UNITS
NAME
MIN.
TYP.
--
MAX.
tAVAX
tAVQX
tE1LQV
tE2LQV
tGLQV
tE1LQX
tE2LQX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
tAVQX
tRC
tAA
55
--
--
55
55
55
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
--
Chip Select Access Time
(CE1)
(CE2)
tACS1
tACS2
tOE
--
--
Chip Select Access Time
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
--
--
(CE1)
(CE2)
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
10
10
5
--
Chip Select to Output Low Z
--
--
Output Enable to Output Low Z
Chip Select to Output High Z
--
--
(CE1)
(CE2)
--
--
25
25
25
--
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
--
--
--
--
10
--
Revision 1.1
R0201-BH62UV1601
4
May
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
