BH616UV1611
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VCC for Data Retention
1.0
--
--
V
VCC=1.2V
Data Retention Current
--
0
1.5
--
15
--
uA
ns
ns
ICCDR
tCDR
tR
Chip Deselect to Data
Retention Time
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
--
1. Typical characteristics are at TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE1≧VCC - 0.2V
VIH
VIH
CE1
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
MUST BE
STEADY
MUST BE
STEADY
Input and Output Timing
Reference Level
0.5Vcc
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1
tCHZ2, tBDO, tOHZ, tWHZ, tOW
,
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
VCC
GND
CHANGE :
STATE UNKNOW
1 TTL
90%
90%
Output
10%
10%
(1)
®
¬
®
¬
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL
DOES NOT
APPLY
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
Revision 1.3
R0201-BH616UV1611
5
Otc.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
