ADS7863
www.ti.com
SBAS383–JUNE 2007
DEVICE INFORMATION
ADS7863IDBQ
SSOP-24 (DBQ)
(TOP VIEW)
ADS7863IRG
4 x 4 QFN-24 (RGE)
(TOP VIEW)
BGND
CHB1+
CHB1-
CHB0+
CHB0-
CHA1+
CHA1-
CHA0+
CHA0-
1
2
3
4
5
6
7
8
9
24 BVDD
23 SDOA
22 SDOB
21 BUSY
20 CLOCK
19 CS
1
2
3
4
5
6
18
17
16
15
14
13
CHA0-
REFIN
CHB1+
BGND
BVDD
REFOUT
ADS7863
AGND
AVDD
SDOA
SDOB
BUSY
18 RD
17 CONVST
16 SDI
M1
REFIN 10
REFOUT 11
AGND 12
15 M0
14 M1
13 AVDD
PIN DESCRIPTIONS
PIN NUMBER
SSOP
QFN
NAME
BGND
CHB1+
CHB1–
CHB0+
CHB0–
CHA1+
CHA1–
CHA0+
CHA0–
REFIN
REFOUT
AGND
AVDD
DESCRIPTION
1
2
17
18
19
20
21
22
23
24
1
Buffer I/O ground. Connect to digital ground plane.
Noninverting analog input channel B1
Inverting analog input channel B1
3
4
Noninverting analog input channel B0
Inverting analog input channel B0
5
6
Noninverting analog input channel A1
Inverting analog input channel A1
7
8
Noninverting analog input channel A0
Inverting analog input channel A0
9
10
11
12
13
14
15
2
Reference voltage input. A ceramic capacitor of 470nF (min) is required at this terminal.
3
Reference voltage output. The programmable internal voltage reference output is available on this pin.
Analog ground. Connect to analog ground plane.
4
5
Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1μF ceramic capacitor.
Mode pin 1. Selects between the SDOx digital outputs (see Table 7).
Mode pin 0. Selects between analog input channels (see Table 7).
6
M1
7
M0
Serial data input. This pin allows the additional features of the ADS7863 to be used but can also be used
in ADS7861-compatible manner.
16
17
8
9
SDI
Conversion start. The ADC switches from the sample into the hold mode on the rising edge of CONVST,
independent of the status of CLOCK.
CONVST
18
19
20
10
11
12
RD
CS
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low.
Chip select. When low, the SDOx outputs are active; when high, the SDOx outputs are tri-stated.
External clock input
CLOCK
ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the
conversion has been finished.
21
22
23
24
13
14
15
16
BUSY
SDOB
SDOA
BVDD
Serial data output for converter B. Data are valid on the falling edge of CLOCK.
Serial data output for converter A. When M1 is high, both SDOA and SDOB are active. Data are valid on
the falling edge of CLOCK.
Buffer I/O supply, 1.65V to 5.5V. Decouple to BGND with a 1μF ceramic capacitor.
6
Submit Documentation Feedback
BB [ BURR-BROWN CORPORATION ]
