PIN DESCRIPTIONS
PIN CONFIGURATION
PIN
NAME
DESCRIPTION
Top View
1
2
REFIN
Reference Input
REFOUT
+2.5V Reference Output. Connect directly to REFIN
(pin 1) when using internal reference.
32 31 30 29 28 27 26 25
3
4
AGND
+VA
Analog Ground
Analog Power Supply, +5VDC. Connect directly to
digital power supply (pin 24). Decouple to analog
ground with a 0.1µF ceramic capacitor and a 10µF
tantalum capacitor.
1
2
3
4
5
6
7
8
24 +VD
REFIN
REFOUT
AGND
+VA
23 DGND
22 A0
5
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BUSY
Data Bit 11, MSB
Data Bit 10
6
21 RD
ADS7862
7
Data Bit 9
20 CS
DB11
DB10
DB9
8
Data Bit 8
19 CLOCK
18 CONVST
17 BUSY
9
Data Bit 7
10
11
12
13
14
15
16
17
18
19
Data Bit 6
Data Bit 5
DB8
Data Bit 4
Data Bit 3
9
10 11 12 13 14 15 16
Data Bit 2
Data Bit 1
Data Bit 0, LSB
HIGH when a conversion is in progress.
CONVST Convert Start
ABSOLUTE MAXIMUM RATINGS
CLOCK
An external CMOS-compatible clock can be applied to
the CLOCK input to synchronize the conversion pro-
cess to an external source. The CLOCK pin controls
Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V)
REFIN ............................. –0.3V to (+VD + 0.3V)
Digital Inputs to DGND.......................................... –0.3V to (+VD + 0.3V)
Ground Voltage Differences: AGND, DGND ................................... ±0.3V
+VD to AGND ......................... –0.3V to +6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
the sampling rate by the equation: CLOCK 16 • fSAMPLE
.
20
21
CS
RD
Chip Select
Synchronization pulse for the parallel output. During a
Read operation, the first falling edge selects the A
register and the second edge selects the B register,
A0, then controls whether input 0 or input 1 is read.
22
A0
On the falling edge of Convert Start, when A0 is LOW
Channel A0 and Channel B0 are converted and when
it is HIGH, Channel A1 and Channel B1 are converted.
During a Read operation, the first falling edge selects
the A register and the second edge selects the B of RD
register, A0, then controls whether input 0 or input 1 is
read.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
23
24
25
26
27
28
29
30
31
32
DGND
+VD
Digital Ground. Connect directly to analog ground (pin 3).
Digital Power Supply, +5VDC
CH B1+ Non-Inverting Input Channel B1
CH B1– Inverting Input Channel B1
CH B0+ Non-Inverting Input Channel B0
CH B0– Inverting Input Channel B0
CH A1– Inverting Input Channel A1
CH A1+ Non-Inverting Input Channel A1
CH A0– Inverting Input Channel A0
CH A0+ Non-Inverting Input Channel A0
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi-
cations.
®
ADS7862
3
BB [ BURR-BROWN CORPORATION ]
