PIN CONFIGURATION
Top View
VFBGA
Top View
SSOP, TSSOP
DCLK
CS
DIN BUSY DOUT
+VCC
X+
1
2
3
4
5
6
7
8
16 DCLK
15 CS
1
2
3
4
5
6
7
A
B
C
D
E
F
NC
NC
Y+
14 DIN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
+VCC
+VCC
X+
PENIRQ
+VCC
X–
13 BUSY
12 DOUT
ADS7846
Y–
NC
NC
NC
GND
VBAT
AUX
11 PENIRQ
10 +VCC
VREF
Y+
AUX
9
VREF
NC
NC
NC
NC
G
X–
Y–
GND GND VBAT
Top View
QFN
BUSY
DIN
1
2
3
4
12 AUX
11 VBAT
10 GND
ADS7846
CS
DCLK
9
Y–
PIN DESCRIPTION
SSOP AND
TSSOP PIN #
VFBGA PIN #
QFN PIN #
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
B1 and C1
5
6
7
8
9
10
11
12
13
14
15
16
+VCC
X+
Y+
X–
Y–
GND
VBAT
AUX
VREF
+VCC
PENIRQ
DOUT
Power Supply
X+ Position Input
Y+ Position Input
X– Position Input
Y– Position Input
Ground
Battery Monitor Input
Auxiliary Input to ADC
Voltage Reference Input/Output
Digital I/O Power Supply
D1
E1
G2
G3
G4 and G5
G6
E7
D7
C7
B7
A6
10
11
12
Pen Interrupt. Open anode output (requires 10kΩ to 100kΩ pull-up resistor externally).
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
13
14
15
A5
A4
A3
1
2
3
BUSY
DIN
CS
Busy Output. This output is high impedance when CS is high.
Serial Data Input. If CS is low, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
16
A2
4
DCLK
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.
ADS7846
4
SBAS125H
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