within the same period, which can be as little as 350ns in
some operating modes. While the converter is in the hold
mode, or after the sampling capacitor has been fully charged,
the input impedance of the analog input is greater than 1GΩ.
THEORY OF OPERATION
The ADS7842 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6µm CMOS process.
EXTERNAL CLOCK
The ADS7842 requires an external clock to run the conver-
sion process. This clock can vary between 200kHz (12.5kHz
throughput) and 3.2MHz (200kHz throughput). The duty
cycle of the clock is unimportant as long as the minimum
HIGH and LOW times are at least 150ns and the clock
period is at least 300ns. The minimum clock frequency is set
by the leakage on the capacitors internal to the ADS7842.
The basic operation of the ADS7842 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+VCC. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7842.
ANALOG INPUTS
BASIC OPERATION
The ADS7842 features four, single-ended inputs. The input
current into each analog input depends on input voltage and
sampling rate. Essentially, the current into the device must
charge the internal hold capacitor during the sample period.
After this capacitance has fully charged, there is no further
input current. The source of the analog input voltage must be
able to charge the input capacitance to a 12-bit settling level
Figure 1 shows the simple circuit required to operate the
ADS7842 with Channel 0 selected. A conversion can be
initiated by bringing the WR pin (pin 22) LOW for a
minimum of 25ns. BUSY (pin 23) will output a LOW during
the conversion process and rises only after the conversion is
complete. The 12 bits of output data will be valid on pins
7-13 and 15-19 following the rising edge of BUSY.
ADS7842
0V to VREF
+5V Analog Supply
1
2
3
4
5
6
7
8
9
AIN0
AIN1
AIN2
AIN3
VREF
VANA 28
VDIG 27
A1 26
+
+
0.1µF
10µF
A0 25
+5V
CLK 24
BUSY 23
WR 22
CS 21
3.2MHz Clock
+
2.2µF
AGND
DB11
DB10
DB9
BUSY Output
Write Input
RD 20
Read Input
10 DB8
11 DB7
12 DB6
13 DB5
14 DGND
DB0 19
DB1 18
DB2 17
DB3 16
DB4 15
FIGURE 1. Basic Operation of the ADS7842.
®
ADS7842
9
BB [ BURR-BROWN CORPORATION ]
