occurs faster than the 10ns indicated by tCKCH, then there is
a chance that some digital feedthrough may be coupled onto
the hold capacitor. This could cause a small offset error for
that particular conversion.
Figure 4 shows the typical method for placing the A/D into
the power-down mode. If CONV is kept LOW during the
conversion and is LOW at the start of the 13 clock cycle,
then the device enters the power-down mode. It remains in
this mode until the rising edge of CONV. Note that CONV
must be HIGH for at least tACQ in order to sample the signal
properly as well as to power-up the internal nodes.
Thus, there are two basic ways to operate the ADS7834.
CONV can be synchronous to CLK and CLK can be con-
tinuous. This would be the typical situation when interfacing
the converter to a digital signal processor. The second
method involves having CONV asynchronous to CLK and
gating the operation of CLK (a non-continuous clock). This
method would be more typical of an SPI-like interface on a
microcontroller. This method would also allow CONV to be
generated by a trigger circuit and to initiate (after some
delay) the start of CLK. These two methods are covered
under DSP Interfacing and SPI Interfacing.
There are two different methods for clocking the ADS7834.
The first involves scaling the CLK input in relation to the
conversion rate. For example, an 8MHz input clock and the
timing shown in Figure 3 results in a 500kHz conversion
rate. Likewise, a 1.6MHz clock would result in a 100kHz
conversion rate. The second method involves keeping the
clock input as close to the maximum clock rate as possible
and starting conversions as needed. This timing is similar to
that shown in Figure 4. As an example, a 50kHz conversion
rate would require 160 clock periods per conversion instead
of the 16 clock periods used at 500kHz.
POWER-DOWN TIMING
The conversion timing shown in Figure 3 does not result in
the ADS7834 going into the power-down mode. If the
conversion rate of the device is high (approaching 500kHz),
then there is very little power that can be saved by using the
power-down mode. However, since the power-down mode
incurs no conversion penalty (the very first conversion is
valid), at lower sample rates, significant power can be saved
by allowing the device to go into power-down mode be-
tween conversions.
The main distinction between the two is the amount of time
that the ADS7834 remains in power-down. In the first mode,
the converter only remains in power-down for a small
number of clock periods (depending on how many clock
periods there are per each conversion). As the conversion
rate scales, the converter always spends the same percentage
of time in power-down. Since less power is drawn by the
digital logic, there is a small decrease in power consump-
tion, but it is very slight. This effect can be seen in the
typical performance curve “Supply Current vs Sample Rate.”
tCVL
tCVCK
CONV
tCKCS
tCKCH
14
15
16
1
2
3
4
11
12
13
14
15
16
1
CLK
(1)
tCKDE
tCKDD
D11
(MSB)
D0
(LSB)
DATA
D10
D9
D2
D1
tACQ
tCVHD
tCKSP
SAMPLE/HOLD
MODE
SAMPLE
HOLD
tCONV
SAMPLE
HOLD
(2)
INTERNAL
CONVERSION
STATE
(
3)
IDLE
IDLE
CONVERSION IN PROGRESS
NOTES: (1) Clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ADS7834, provided that the
minimum tACQ time is met. The CLK input may remain HIGH or LOW during this period. (2) The transition from sample mode to hold
mode occurs on the falling edge of CONV. This transition is not dependent on CLK. (3) The device remains fully powered when
operated as shown. If the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device to
enter a power-down mode. See the power-down timing for more information.
FIGURE 3. Basic Conversion Timing.
ADS7834
SBAS098A
9
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