straight binary (with 0V = 000 hex, 5V = FFF hex), and the
data is presented in a right-justified format (with the LSB as
the most right bit in the 16-bit word). Two read operations
are required to transfer the High byte and Low byte, and the
bytes are presented according to the input level on the High
Byte Enable pin (HBE).
The bytes can be read in either order, depending on the status
of the HBE input. If HBE changes while CS and RD are
LOW, the output data will change to correspond to the HBE
input. Figure 4 shows the timing for reading first the Low
byte and then the High byte.
1
2
3
4
5
6
7
16
17
18
CLK
WR
Multiplexer Settling,
Offset Auto Zeroing
and Sampling Acquisition
Successive
Approximation
Conversion
BUSY
FIGURE 2. Converter Timing.
CS
t1
t2
t3
WR or CAL
BUSY
t4
t5
t6
SFR
VIH
VIL
A0, A1
FIGURE 3. Write Cycle Timing (for initiating conversion or calibration).
BUSY
t7
CS
t8
t9
t10
t8
t10
RD
SFR
t11
t12
t11
t12
HBE
t13
t14
Low Byte Data
t13
t14
High Byte Data
Hi-Z State
Hi-Z
D0 - D7
FIGURE 4. Read Cycle Timing.
®
9
ADS7832
BB [ BURR-BROWN CORPORATION ]
