SPECIFICATIONS (CONT)
ELECTRICAL
At TA = –40°C to +85°C, fS = 40kHz, VS1 = VS2 = VS = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.
ADS7825P, U
TYP
ADS7825PB, UB
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
Data Clock
Internal Clock (Output only when
transmitting data)
External Clock
PAR/SER = +5V
PAR/SER = +5V
PAR/SER = 0V
EXT/INT LOW
83
83
✻
✻
ns
ns
0.5
0.1
1.5
10
✻
✻
✻
✻
MHz
MHz
EXT/INT HIGH
POWER SUPPLIES
VS1 = VS2 = VS
Power Dissipation
+4.75
+5
50
+5.25
50
✻
✻
✻
✻
✻
V
mW
µW
fS = 40kHz
PWRD HIGH
TEMPERATURE RANGE
Specified Performance
Storage
–40
–65
+85
+150
✻
✻
✻
✻
°C
°C
Thermal Resistance (θJA
)
Plastic DIP
SOIC
75
75
✻
✻
°C/W
°C/W
NOTES: (1) An asterik (✻) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 16-bit, ±10V input ADS7825, one LSB is 305µV. (3)
Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and
last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred
to a full-scale ±10V input. (6) A full scale sinewave input on one channel will be attenuated by this amount on the other channels. (7) Useable Bandwidth defined as
Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (8) The ADS7825 will accurately acquire any input step if given
a full acquisition period after the step. (9) Recovers to specified performance after 2 x FS input overvoltage, and normal acquisitions can begin.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
MINIMUM SIGNAL-
TO-(NOISE + DISTORTION)
RATIO (dB)
TEMPERATURE
RANGE
MAXIMUM INTEGRAL
LINEARITY ERROR (LSB)
PRODUCT
PACKAGE
ADS7825P
ADS7825PB
ADS7825U
ADS7825UB
Plastic Dip
Plastic Dip
SOIC
246
246
217
217
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±3
±2
±3
±2
83
86
83
86
SOIC
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
TOP VIEW
DIP/SOIC
Analog Inputs: AIN0, AIN1, AIN2, AIN3 .............................................. ±15V
REF ................................... (AGND2 –0.3V) to (VS + 0.3V)
CAP ........................................Indefinite Short to AGND2,
Momentary Short to VS
1
2
3
4
5
6
7
8
9
28
27
VS1
VS2
AGND1
AIN0
VS1 and VS2 to AGND2........................................................................... 7V
VS1 to VS2 .......................................................................................... ±0.3V
Difference between AGND1, AGND2 and DGND ............................. ±0.3V
Digital Inputs and Outputs.......................................... –0.3V to (VS + 0.3V)
Maximum Junction Temperature ..................................................... 150°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s)................................................ +300°C
Maximum Input Current to Any Pin ................................................. 100mA
AIN1
26 PWRD
25 CONTC
24 BUSY
23 CS
AIN2
AIN3
CAP
REF
22 R/C
ADS7825
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
AGND2
D7
21 BYTE
20 PAR/SER
19 A0
TRI-STATE
TRI-STATE
TRI-STATE
EXT/INT
D6 10
D5 11
18 A1
D4 12
17 D0
TAG
16 D1
SYNC
D3 13
SDATA
DATACLK
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
DGND 14
15 D2
®
ADS7825
3
BB [ BURR-BROWN CORPORATION ]
