t1
t1
R/C
t3
t3
t4
BUSY
t5
t6
t6
t7
t8
Convert
Acquire
Convert
t12
Acquire
MODE
t12
t11
t10
Parallel
Data Bus
Previous
High Byte Valid
Previous High
Byte Valid
Previous Low
Byte Valid
High Byte
Valid
Low Byte
Valid
High Byte
Valid
Hi-Z
Not Valid
Hi-Z
t9
t2
t12
t12
t9
t12
t12
BYTE
FIGURE 2. Conversion Timing with Parallel Output (CS LOW).
t21
t21
t21
t21
t21
t21
R/C
CS
t1
t3
t4
BUSY
BYTE
t21
t21
t21
t21
DATA
BUS
Hi-Z State
High Byte Hi-Z State Low Byte
t12 t9 t12
Hi-Z State
t9
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
t7 + t8
CS or R/C(1)
DATACLK
t14
1
2
3
11
12
1
2
t13
t16
t15
SDATA
BUSY
MSB Valid
Bit 10 Valid
Bit 9 Valid
Bit 1 Valid
LSB Valid
MSB Valid
Bit 10 Valid
Hi-Z
Hi-Z
t25
(Results from previous conversion.)
t26
NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW).
®
ADS7824
9
BB [ BURR-BROWN CORPORATION ]
