TIMING CHARACTERISTICS(1)
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
SCL Clock Frequency
fSCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max
High-Speed Mode, CB = 400pF max
100
400
3.4
kHz
kHz
MHz
MHz
1.7
Bus Free Time Between a STOP and
START Condition
tBUF
Standard Mode
Fast Mode
4.7
1.3
µs
µs
Hold Time (Repeated) START
Condition
tHD;STA
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
LOW Period of the SCL Clock
tLOW
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.7
1.3
160
320
µs
µs
ns
ns
HIGH Period of the SCL Clock
tHIGH
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.0
600
60
µs
ns
ns
ns
120
Setup Time for a Repeated START
Condition
tSU;STA
Standard Mode
Fast Mode
High-Speed Mode
4.7
600
160
µs
ns
ns
Data Setup Time
Data Hold Time
tSU DAT
;
Standard Mode
Fast Mode
High-Speed Mode
250
100
10
ns
ns
ns
tHD;DAT
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
0
0
0(3)
0(3)
3.45
0.9
70
µs
µs
ns
ns
150
Rise Time of SCL Signal
tRCL
tRCL1
tFCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
40
ns
ns
ns
ns
20 + 0.1CB
10
20
80
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
300
300
40
ns
ns
ns
ns
20 + 0.1CB
10
20
80
tRDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
tFDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
300
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
tSU;STO
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
Capacitive Load for SDA and SCL
Line
CB
tSP
400
pF
Pulse Width of Spike Suppressed
Fast Mode
50
10
ns
ns
High-Speed Mode
Noise Margin at the HIGH Level for
Each Connected Device (Including
Hysteresis)
Standard Mode
Fast Mode
High-Speed Mode
VNH
0.2VDD
0.1VDD
V
V
Noise Margin at the LOW Level for
Each Connected Device (Including
Hysteresis)
Standard Mode
Fast Mode
High-Speed Mode
VNL
NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with
a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7823
SBAS180B
5
BB [ BURR-BROWN CORPORATION ]
