TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.20
0.15
V
CC = 5V
Change in Integral
Linearity (LSB)
0.10
0.05
0.00
–0.05
–0.10
Change in Differential
Linearity (LSB)
1
10
100
1000
10000
1
2
3
4
5
Ripple Frequency (kHz)
Reference Voltage (V)
ANALOG INPUT
THEORY OF OPERATION
The +In and –In input pins allow for a differential input
signal. Unlike some converters of this type, the –In input is
not re-sampled later in the conversion cycle. When the
converter goes into the hold mode, the voltage difference
between +In and –In is captured on the internal capacitor
array.
The ADS7822 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. The architecture and process allow the
ADS7822 to acquire and convert an analog signal at up to
75,000 conversions per second while consuming very little
power.
The range of the –In input is limited to –0.2V to +1V.
Because of this, the differential input can be used to reject
only small signals that are common to both inputs. Thus, the
–In input is best used to sense a remote signal ground that
may move slightly with respect to the local ground potential.
The ADS7822 requires an external reference, an external
clock, and a single power source (VCC). The external refer-
ence can be any voltage between 50mV and VCC. The value
of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS7822.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power down mode. Essentially, the current into the ADS7822
charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no
further input current. The source of the analog input voltage
must be able to charge the input capacitance (25pF) to a
12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
down mode, the input impedance is greater than 1GΩ.
The external clock can vary between 10kHz (625Hz through-
put) and 1.2MHz (75kHz throughput). The duty cycle of the
clock is essentially unimportant as long as the minimum high
and low times are at least 400ns (VCC = 2.7V or greater).
The minimum clock frequency is set by the leakage on the
capacitors internal to the ADS7822.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –In
input should not drop below GND – 200mV or exceed
GND + 1V. The +In input should always remain within the
range of GND – 200mV to VCC + 200mV. Outside of these
ranges, the converter’s linearity may not meet specifications.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS7822 after the conversion is complete and to obtain the
serial data least significant bit first. See the digital timing
section for more information.
®
ADS7822
7
BB [ BURR-BROWN CORPORATION ]
