CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7820 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (5.4µs max) will initiate a conversion.
BUSY (pin 26) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Straight Binary with the MSB
on pin 6. BUSY going HIGH can be used to latch the data.
All convert commands will be ignored while BUSY is
LOW.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. However,
the output will become active whenever R/C goes HIGH.
Refer to the Reading Data section.
The ADS7820 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal.
CS
1
R/C BUSY OPERATION
X
0
X
1
None. Databus is in Hi-Z state.
↓
Initiates conversion “n”. Databus remains
in Hi-Z state.
0
0
↓
↓
0
0
↓
1
1
1
↑
0
1
↑
1
0
0
↑
Initiates conversion “n”. Databus enters Hi-Z
state.
STARTING A CONVERSION
Conversion “n” completed. Valid data from
conversion “n” on the databus.
The combination of CS (pin 25) and R/C (pin 24) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7820 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without suffi-
cient time to acquire a new signal.
Enables databus with valid data from
conversion “n”.
Enables databus with valid data from
conversion “n-1”(1). Conversion n in process.
Enables databus with valid data from
conversion “n-1”(1). Conversion “n” in process.
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
The ADS7820 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
X
X
0
New convert commands ignored. Conversion
“n” in process.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
Table I. Control Line Functions for “Read” and “Convert”.
0 to +5V
1
2
28
+5V
27
26
25
24
23
22
21
20
19
18
17
16
15
+
+
0.1µF
10µF
2.2µF
+
+
3
4
2.2µF
Convert Pulse
5
B11 (MSB)
6
B10
B9
B8
B7
B6
B5
B4
LOW
7
40ns min
ADS7820
5.4µs max
LOW
LOW
LOW
B0 (LSB)
B1
8
9
10
11
12
13
14
B2
B3
FIGURE 1. Basic Operation (Byte Low).
®
6
ADS7820
BB [ BURR-BROWN CORPORATION ]
