t1
R/C
t12
t2
t3
t5
t4
BUSY
MODE
t6
Convert
t7
Acquire
t8
Convert
Acquire
2
Hi-Z State
Data Valid
t10
Hi-Z State
DATA BUS
Data Valid
t9
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
t11
t11
t11
t11
R/C
CS
t1
t3
t5
t4
BUSY
t6
Convert
t7
Acquire
Acquire
MODE
t2
DATA
BUS
Hi-Z State
Data Valid Hi-Z State
t9
t13
FIGURE 3. Using CS to Control Conversion and Read Timing.
50Ω
50Ω
VIN
VIN
VIN
VIN
+5V
R1
20kΩ
AGND1
REF
AGND1
REF
P1
5kΩ
R2
604kΩ
+5V
–5V
0.1µF
10µF
P2
5kΩ
0.1µF
10µF
CAP
CAP
+
+
AGND2
AGND2
NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim
gain at 2.5V.
FIGURE 4b. Circuit Diagram Without External Hardware
Trim.
FIGURE 4a. Circuit Diagram With External Hardware Trim.
®
9
ADS7819
BB [ BURR-BROWN CORPORATION ]
