internal reference. This reference can be used to supply a
small amount of source current to an external load, but the
load should be static. Due to the internal 10kΩ resistor, a
dynamic load will cause variations in the reference voltage,
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage
seen at the buffer input. The amount of reduction depends on
the load and the actual value of the internal “10kΩ” resistor.
The value of this resistor can vary by ±30%.
tCKP
tCKH
tCKL
CLK
tCKDS
tCKDH
DATA
FIGURE 2. Serial Data and Clock Timing.
The VREF pin should be bypassed with a 0.1µF capacitor
placed as close as possible to the ADS7818 package. In
addition, a 2.2 µF tantalum capacitor should be used in
parallel with the ceramic capacitor. Placement of this ca-
pacitor is not as critical.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tCONV
tCKP
Acquisition Time
Conversion Time
Clock Period
Clock LOW
350
1.5
125
50
ns
µs
ns
ns
ns
ns
5000
tCKL
EXTERNAL REFERENCE
tCKH
Clock HIGH
50
The internal reference is connected to the VREF pin and to the
internal buffer via a 10kΩ series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.0V
to 2.55V, corresponding to an analog input range of 4.0V to
5.1V.
tCKDH
Clock Falling to Current Data
Bit No Longer Valid
5
15
30
tCKDS
tCVL
Clock Falling to Next Data Valid
CONV LOW
50
ns
ns
ns
ns
ns
ns
ns
40
40
10
10
tCVH
CONV HIGH
tCKCH
tCKCS
tCKDE
tCKDD
CONV Hold after Clock Falls(1)
CONV Setup to Clock Falling(1)
Clock Falling to DATA Enabled
While the external reference will not source significant
current into the VREF pin, it does have to drive the series
10kΩ resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
±30% from part to part). In addition, the VREF pin should
still be bypassed to ground with at least a 0.1 µF ceramic
capacitor (placed as close to the ADS7818 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2µF tantalum capacitor shown in Figure 1.
20
70
50
Clock Falling to DATA
High Impedance
100
tCKSP
tCKPD
tCVHD
Clock Falling to Sample Mode
5
50
5
ns
ns
ns
Clock Falling to Power-down Mode
CONV Falling to Hold Mode
(Aperture Delay)
tCVSP
tCVPU
tCVDD
CONV Rising to Sample Mode
CONV Rising to Full Power-up
5
ns
ns
ns
50
70
CONV Changing State to DATA
High Impedance
100
5
tCVPD
CONV Changing State to
Power-down Mode
50
ns
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. For example, a 2.048V refer-
ence provides for a 0V to 4.095V input range—or 1mV per
LSB. The other is to provide greater stability over tempera-
ture. The internal reference is typically 20ppm/°C which
translates into a full-scale drift of roughly 1 output code for
every 12°C (this does not take into account other sources of
full-scale drift). If greater stability over temperature is needed,
then an external reference with lower temperature drift will
be required.
tDRP
CONV Falling to Start of CLK
(for hold droop < 0.1 LSB)
µs
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (TA = –40°C to +85°C,
CLOAD = 30pF).
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (tCKCH and tCKCS). However, if these times
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high-imped-
ance and goes LOW, the conversion has started and that
clock cycle is this first of the conversion.)
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7818. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
In addition if CONV is completely asynchronous to CLK
and CLK is continuous, then there is possibility that CLK
will transition just prior to CONV going LOW. If this occurs
®
ADS7818
8
BB [ BURR-BROWN CORPORATION ]
