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ADS7812UB 参数 Datasheet PDF下载

ADS7812UB图片预览
型号: ADS7812UB
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗,串行12位采样模拟数字转换器 [Low-Power, Serial 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 17 页 / 383 K
品牌: BB [ BURR-BROWN CORPORATION ]
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EXTERNAL DATACLK  
BASIC OPERATION  
Figure 1b shows a basic circuit to operate the ADS7812 with  
a ±10V input range. To begin a conversion, a falling edge  
must be provided to the CONV input. BUSY will go LOW  
indicating that a conversion has started and will stay LOW  
until the conversion is complete. Just prior to BUSY rising  
near the end of the conversion, the internal working register  
holding the conversion result will be transferred to the  
internal shift register.  
INTERNAL DATACLK  
Figure 1a shows a basic circuit to operate the ADS7812 with  
a ±10V input range. To begin a conversion and serial  
transmission of the results from the previous conversion, a  
falling edge must be provided to the CONV input. BUSY  
will go LOW indicating that a conversion has started and  
will stay LOW until the conversion is complete. During the  
conversion, the results of the previous conversion will be  
transmitted via DATA while DATACLK provides the syn-  
chronous clock for the serial data. The data format is 12-bit,  
Binary Two’s Complement, and MSB first. Each data bit is  
valid on both the rising and falling edge of DATACLK.  
BUSY is LOW during the entire serial transmission and can  
be used as a frame synchronization signal.  
The internal shift register is clocked via the DATACLK  
input. The recommended method of reading the conversion  
result is to provide the serial clock after the conversion has  
completed. See External DATACLK under the Reading  
Data section of this data sheet for more information.  
C1  
C2  
ADS7812  
0.1µF 10µF  
+5V  
±10V  
1
2
3
4
5
6
7
8
R1IN  
GND  
R2IN  
R3IN  
BUF  
CAP  
REF  
GND  
VS 16  
PWRD 15  
BUSY 14  
CS 13  
+
Frame Sync (optional)  
Convert Pulse  
CONV 12  
EXT/INT 11  
DATA 10  
+
C3  
C4  
0.01µF  
1µF  
+
C5  
1µF  
40ns min  
DATACLK  
9
FIGURE 1a. Basic Operation, ±10V Input Range, Internal DATACLK.  
C1  
C2  
ADS7812  
0.1µF 10µF  
+5V  
±10V  
1
2
3
4
5
6
7
8
R1IN  
GND  
R2IN  
R3IN  
BUF  
CAP  
REF  
GND  
VS 16  
PWRD 15  
BUSY 14  
CS 13  
+
Interrupt (optional)  
Chip Select (optional(1)  
)
Convert Pulse  
CONV 12  
EXT/INT 11  
DATA 10  
+
C3  
C4  
0.01µF  
+5V  
1µF  
+
40ns min  
C5  
1µF  
External Clock  
DATACLK  
9
NOTE: (1) Tie CS to GND if the outputs will always be active.  
FIGURE 1b. Basic Operation, ±10V Input Range, External DATACLK.  
®
7
ADS7812