STARTING A CONVERSION
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t1
t2
Conversion Plus Acquisition Time
25
8
µs
µs
If a conversion is not currently in progress, a falling edge on
the CONV input places the sample and hold into the hold
mode and begins a conversion, as shown in Figure 2 and
with the timing given in Table II. During the conversion, the
CONV input is ignored. Starting a conversion does not
depend on the state of CS. A conversion can be started once
every 25µs (40kHz maximum conversion rate). There is no
minimum conversion rate.
CONV LOW to All Digital
Inputs Stable
t3
t4
CONV LOW to Initiate a Conversion 40
ns
ns
BUSY Rising to Any Digital
Input Active
0
t5
CONV HIGH Prior to Start
of Conversion
2
µs
t6
t7
BUSY LOW
CONV LOW to BUSY LOW
Aperture Delay
15
85
40
14
1.1
20
µs
ns
ns
µs
µs
120
Even though the CONV input is ignored while a conversion
is in progress, this input should be held static during the
conversion period. Transitions on this digital input can
easily couple into sensitive analog portions of the converter,
adversely affecting the conversion results (see the Sensitiv-
ity to External Digital Signals section of this data sheet for
more information).
t8
t9
Conversion Time
20
2
t10
Conversion Complete to
BUSY Rising
t11
t12
Acquisition Time
5
µs
µs
CONV LOW to Rising Edge
of First DATACLK
1.4
t13
t14
t15
t16
Internal DATACLK HIGH
Internal DATACLK LOW
Internal DATACLK Period
250 350 500
ns
ns
µs
ns
Ideally, the CONV input should go LOW and remain LOW
throughout the conversion. It should return HIGH sometime
after BUSY goes HIGH. In addition, it should be HIGH
prior to the start of the next conversion for a minimum time
period given by t5. This will ensure that the digital transition
on the CONV input will not affect the signal that is acquired
for the next conversion.
600 760 875
1.1
20
DATA Valid to Internal
DATACLK Rising
t17
t18
t19
t20
Internal DATACLK Falling
to DATA Not Valid
400
800
15
ns
ns
ns
ns
Falling Edge of Last DATACLK
to BUSY Rising
An acceptable alternative is to return the CONV input HIGH
as soon as possible after the start of the conversion. For
example, a negative going pulse 100ns wide would make a
good CONV input signal. It is strongly recommended that
from time t2 after the start of a conversion until BUSY rises,
the CONV input should be held static (either HIGH or
LOW). During this time, the converter is more sensitive to
external noise.
External DATACLK Rising
to DATA Not Valid
External DATACLK Rising
to DATA Valid
55
85
t21
t22
t23
t24
External DATACLK HIGH
External DATACLK LOW
External DATACLK Period
50
50
ns
ns
ns
ns
100
120
CONV LOW to External
DATACLK Active
t25
External DATACLK LOW
2
µs
or CS HIGH to BUSY Rising
t26
t27
CS LOW to Digital Outputs Enabled
85
ns
ns
CS HIGH to Digital Outputs Disabled 85
TABLE II. ADS7812 Timing. TA = –40°C to +85°C.
t1
t2
t3
t4
t5
CONV
t6
t7
BUSY
t8
t10
t9
t11
MODE
Acquire
Convert
Acquire
Convert
FIGURE 2. Basic Conversion Timing.
®
ADS7812
8
BB [ BURR-BROWN CORPORATION ]
