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ADS7808_07 参数 Datasheet PDF下载

ADS7808_07图片预览
型号: ADS7808_07
PDF下载: 下载PDF文件 查看货源
内容描述: 12位10us的串行CMOS采样模拟到数字转换器 [12-Bit 10us Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 13 页 / 329 K
品牌: BB [ BURR-BROWN CORPORATION ]
 浏览型号ADS7808_07的Datasheet PDF文件第2页浏览型号ADS7808_07的Datasheet PDF文件第3页浏览型号ADS7808_07的Datasheet PDF文件第4页浏览型号ADS7808_07的Datasheet PDF文件第5页浏览型号ADS7808_07的Datasheet PDF文件第7页浏览型号ADS7808_07的Datasheet PDF文件第8页浏览型号ADS7808_07的Datasheet PDF文件第9页浏览型号ADS7808_07的Datasheet PDF文件第10页  
SPECIFIC FUNCTION  
CS  
R/C  
BUSY EXT/INT DATACLK PWRD SB/BTC  
OPERATION  
Initiate Conversion and  
Output Data Using  
Internal Clock  
1>0  
0
1
0
Output  
0
x
Initiates conversion n. Data from conversion n1”  
clocked out on DATA synchronized to 12 clock  
pulses output on DATACLK.  
0
1>0  
1
0
Output  
0
x
Initiates conversion n. Data from conversion n1”  
clocked out on DATA synchronized to 12 clock  
pulses output on DATACLK.  
Initiate Conversion and  
Output Data Using External  
Clock  
1>0  
0
0
1>0  
1
1
1
1
1
1
1
Input  
Input  
Input  
0
0
x
x
x
x
Initiates conversion n.  
Initiates conversion n.  
1>0  
Outputs a pulse on SYNC followed by data from  
conversion nclocked out synchronized to external  
DATACLK.  
1>0  
0
1
0>1  
0
0
0
1
1
x
Input  
Input  
x
0
0
0
x
x
x
Outputs a pulse on SYNC followed by data from  
conversion n1clocked out synchronized to  
external DATACLK.(1) Conversion nin process.  
Outputs a pulse on SYNC followed by data from  
conversion n1clocked out synchronized to  
external DATACLK .(1) Conversion nin process.  
Incorrect Conversions  
Power Down  
0
0>1  
CS or R/C must be HIGH or a new conversion will  
be initiated without time for acquisition.  
x
x
x
x
x
x
x
x
x
x
0
1
x
x
Analog circuitry powered. Conversion can proceed.  
Analog circuitry disabled. Data from previous  
conversion maintained in output registers.  
x
x
x
x
x
x
x
x
x
x
x
x
0
1
Serial data is output in Binary Twos Complement  
format.  
Selecting Output Format  
Serial data is output in Straight Binary format.  
NOTE: (1) See Figure 3b for constraints on previous data valid during conversion.  
Table III. Control Truth Table.  
DIGITAL OUTPUT  
BINARY TWOS  
COMPLEMENT  
(SB/BTC LOW)  
STRAIGHT BINARY  
(SB/BTC HIGH)  
HEX  
HEX  
DESCRIPTION  
ANALOG INPUT  
BINARY CODE  
CODE  
BINARY CODE CODE  
Full-Scale Range  
Least Significant Bit (LSB)  
+Full Scale (FS 1LSB)  
Midscale  
±10  
±5  
±3.33V  
0V to 5V 0V to 10V  
1.22mV 2.44mV  
0V to 4V  
0.98mV  
4.88mV  
2.44mV  
1.63mV  
9.99512V 4.99756V 3.33171V 4.99878V 9.99756V  
0V 0V 0V 2.5V 5V  
4.88mV 2.44mV 1.63mV 2.49878V 4.99756V  
10V 5V 3.333333V 0V 0V  
3.99902V 0111 1111 1111  
2V 0000 0000 0000  
1.99902V 1111 1111 1111  
0V 1000 0000 0000  
7FF  
000  
FFF  
800  
1111 1111 1111  
FFF  
1000 0000 0000 800  
0111 1111 1111 7FF  
0000 0000 0000 000  
One LSB Below Midscale  
Full Scale  
Table IV. Output Codes and Ideal Input Voltages.  
ADS7808  
6
SBAS018A  
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