PIN ASSIGNMENTS
PIN #
NAME
R1IN
DESCRIPTION
1
2
3
4
5
6
Analog Input. See Table I and Figure 4 for input range connections.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Analog Input. See Table I and Figure 4 for input range connections.
Analog Input. See Table I and Figure 4 for input range connections.
Reference Buffer Capacitor. 2.2µF Tantalum to ground.
AGND1
R2IN
R3IN
CAP
REF
Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,
bypass to ground with a 2.2µF Tantalum capacitor.
7
8
AGND2
SB/BTC
Analog Ground.
Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If
LOW, data will be output in a Binary Two’s complement format.
9
EXT/INT
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If
LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output
on DATACLK.
10
11
DGND
SYNC
Digital Ground.
Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a
pulse on SYNC synchronized to the external DATACLK.
12
13
DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,
DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions.
DATA
Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock
mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If
EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the
level of the TAG input when the conversion was started.
14
15
TAG
R/C
Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12
DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a
rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
16
17
CS
Chip Select. Internally OR’ed with R/C.
BUSY
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.
18
19
20
PWRD
VANA
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous
conversion are maintained in the output shift register.
Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA
.
PIN CONFIGURATION
ANALOG CONNECT R1IN CONNECT R2IN
INPUT
RANGE
VIA 200Ω
TO
VIA 100Ω
TO
CONNECT R3IN
TO
IMPEDANCE
R1IN
AGND1
R2IN
1
2
3
4
5
6
7
8
9
20 VDIG
±10V
±5V
±3.33
0V to 10V
0V to 5V
0V to 4V
VIN
AGND
VIN
AGND
AGND
VIN
AGND
VIN
VIN
VIN
AGND
AGND
CAP
CAP
CAP
AGND
VIN
22.9kΩ
13.3kΩ
10.7kΩ
13.3kΩ
10.0kΩ
10.7kΩ
19 VANA
18 PWRD
17 BUSY
16 CS
R3IN
VIN
CAP
ADS7808
TABLE I. Input Range Connections. See Figure 4 for
complete information.
REF
15 R/C
AGND2
SB/BTC
EXT/INT
14 TAG
13 DATA
12 DATACLK
11 SYNC
DGND 10
ADS7808
4
SBAS018A
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