ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified.
ADS7808U
TYP
ADS7808UB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
40
ꢀ
ꢀ
ns
ns
µs
ns
Sufficient to meet AC specs
FS Step
No Load
2
ꢀ
ꢀ
150
ꢀ
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer)
External Reference Voltage Range
for Specified Linearity
2.48
2.3
2.5
1
2.52
ꢀ
ꢀ
ꢀ
ꢀ
V
µA
2.5
2.7
ꢀ
ꢀ
ꢀ
V
External Reference Current Drain
Ext. 2.5000V Ref
100
µA
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
+0.8
VD +0.3V
±10
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
(8)
VIL = 0V
VIH = 5V
IIH
±10
DIGITAL OUTPUTS
Data Format
Data Coding
Pipeline Delay
Data Clock
Serial 12 bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
Internal
EXT/INT LOW
EXT/INT HIGH
2.3
ꢀ
MHz
MHz
(Output Only When
Transmitting Data)
External
0.1
+4
10
+0.4
±5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
15
(Can Run Continually)
VOL
VOH
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
OUT = 0V to VDIG
High-Z State
V
V
µA
Leakage Current
V
Output Capacitance
15
pF
V
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Must be ≤ VANA
+4.75
+5
0.3
+5
+5.25
+5.25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
mA
mA
ꢀ
+4.75
16
Power Dissipation: PWRD LOW
PWRD HIGH
VDIG = VANA = 5V, fS = 100kHz
100
mW
µW
50
ꢀ
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
–40
–55
–65
+85
+125
+150
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
°C
°C
°C
Thermal Resistance (θJA
)
SO
75
ꢀ
°CW
ꢀ Specifications same as ADS7808U.
NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of
–Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and
includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum VIH level for the DATACLK
signal is 3V.
ADS7808
SBAS018A
3
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BB [ BURR-BROWN CORPORATION ]
