clock pulse. As a result, data can be read on the parallel port
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.
PARALLEL OUTPUT (AFTER A CONVERSION)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13 and
15-17). BUSY going high can be used to latch the data. Refer
to Table V and Figures 2 and 3 for timing constraints.
PARALLEL OUTPUT
To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when R/C (pin
22) is HIGH and CS (pin 23) is LOW. Any other combination
of CS and R/C will tri-state the parallel output. Valid conver-
sion data can be read in two 8-bit bytes on D7-D0 (pins 9-13
and 15-17). When BYTE (pin 21) is LOW, the 8 most signifi-
cant bits will be valid with the MSB on D7. When BYTE is
HIGH, the 8 least significant bits will be valid with the LSB on
D0. BYTE can be toggled to read both bytes within one
conversion cycle.
PARALLEL OUTPUT (DURING A CONVERSION)
After conversion ‘n’ has been initiated, valid data from con-
version ‘n – 1’ can be read and will be valid up to 12µs after
the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY (pin
24) goes HIGH; this may result in reading invalid data. Refer
to Table V and Figures 2 and 3 for timing constraints.
Upon initial power up, the parallel output will contain indeter-
minate data.
t1
t1
R/C
t3
t3
t4
BUSY
t5
t6
t6
t7
t8
Acquire
Convert
Convert
t12
Acquire
MODE
t12
t11
t10
Parallel
Data Bus
Previous
High Byte Valid
Previous High
Byte Valid
Previous Low
Byte Valid
High Byte
Valid
Low Byte
Valid
High Byte
Valid
Hi-Z
Not Valid
Hi-Z
t9
t2
t12
t12
t9
t12
t12
BYTE
FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).
t21
t21
t21
t21
t21
t21
R/C
CS
t1
t3
t4
BUSY
BYTE
t21
t21
t21
t21
DATA
BUS
Hi-Z State
High Byte Hi-Z State Low Byte
t12 t9 t12
Hi-Z State
t9
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
ADS7807
SBAS022C
9
www.ti.com
BB [ BURR-BROWN CORPORATION ]
