LOW for 40ns (12µs max) will initiate a conversion and
output valid data from the previous conversion on SDATA
(pin 19) synchronized to 12 clock pulses output on DATACLK
(pin 18). BUSY (pin 24) will go LOW and stay LOW until the
conversion is completed and the serial data has been trans-
mitted. Data will be output in BTC format, MSB first, and will
be valid on both the rising and falling edges of the data clock.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
BASIC OPERATION
PARALLEL OUTPUT
Figure 1a shows a basic circuit to operate the ADS7806 with
a ±10V input range and parallel output. Taking R/C (pin 22)
LOW for 40ns (12µs max) will initiate a conversion. BUSY
(pin 24) will go LOW and stay LOW until the conversion is
completed and the output register is updated. If BYTE (pin
21) is LOW, the eight Most Significant Bits (MSBs) will be
valid when BUSY rises; if BYTE is HIGH, the four Least
Significant Bits (LSBs) will be valid when BUSY rises. Data
will be output in Binary Two’s Complement (BTC) format.
BUSY going HIGH can be used to latch the data. After the
first byte has been read, BYTE can be toggled allowing the
remaining byte to be read. All convert commands will be
ignored while BUSY is LOW.
The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com-
mands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
section).
The ADS7806 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com-
mands assures accurate acquisition of a new signal.
STARTING A CONVERSION
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
section).
The combination of CS (pin 23) and R/C (pin 22) LOW for a
minimum of 40ns immediately puts the sample-and-hold of
the ADS7806 in the hold state and starts conversion ‘n’.
BUSY (pin 24) will go LOW and stay LOW until conversion
‘n’ is completed and the internal output register has been
updated. All new convert commands during BUSY LOW will
be ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH, or a new conversion will be initiated without sufficient
time to acquire a new signal.
SERIAL OUTPUT
Figure 1b shows a basic circuit to operate the ADS7806 with
a ±10V input range and serial output. Taking R/C (pin 22)
Parallel Output
Serial Output
200Ω
200Ω
±10V
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
±10V
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1µF 10µF
0.1µF 10µF
+5V
+
+
66.5kΩ
2.2µF
+5V
+
+
66.5kΩ
2.2µF
3
+5V
3
100Ω
2.2µF
4
100Ω
2.2µF
BUSY
4
5
+
+
+5V
BUSY
R/C
Convert Pulse
40ns min
5
6
+
+
R/C
Convert Pulse
40ns min
7
6
ADS7806
BYTE
8
7
ADS7806
9
8
NC(1)
10
11
12
13
14
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
9
SDATA
10
11
12
13
14
DATACLK
NC(1)
NC(1)
NC(1)
Pin 21 B11 B10 B9 B8 B7
LOW (MSB)
B6 B5 B4
LOW LOW LOW
Pin 21 B3 B2 B1 B0 LOW
HIGH (LSB)
NOTE: (1) These pins should be left unconnected.
They will be active when R/C is HIGH.
NOTE: (1) SDATA (pin 19) is always active.
FIGURE 1b. Basic ±10V Operation with Serial Output.
FIGURE 1a. Basic ±10V Operation, both Parallel and Serial
Output.
ADS7806
SBAS021B
7
www.ti.com
BB [ BURR-BROWN CORPORATION ]
