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ADS7805UB/1K 参数 Datasheet PDF下载

ADS7805UB/1K图片预览
型号: ADS7805UB/1K
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO28, GREEN, PLASTIC, SOIC-28]
分类和应用: 光电二极管转换器
文件页数/大小: 20 页 / 586 K
品牌: BB [ BURR-BROWN CORPORATION ]
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PARALLEL OUTPUT (During a Conversion)  
READING DATA  
After conversion nhas been initiated, valid data from con-  
version n 1can be read and will be valid up to 7µs after  
the start of conversion n. Do not attempt to read data from  
7µs after the start of conversion nuntil BUSY (pin 26) goes  
HIGH; this may result in reading invalid data. Refer to Table  
IV and Figures 3 to 5 for timing specifications.  
The ADS7805 outputs full or byte-reading parallel data in  
Binary Twos Complement data output format. The parallel  
output will be active when R/C (pin 24) is HIGH and CS (pin  
25) is LOW. Any other combination of CS and R/C will tri-  
state the parallel output. Valid conversion data can be read  
in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13  
and pins 15-22. BYTE (pin 23) can be toggled to read both  
bytes within one conversion cycle. Refer to Table III for ideal  
output codes and Figure 2 for bit locations relative to the  
state of BYTE.  
Note! For the best possible performance, data should not be  
read during a conversion. The switching noise of the asyn-  
chronous data transfer can cause digital feedthrough de-  
grading the converters performance.  
The number of control lines can be reduced by tying CS LOW  
while using R/C to initiate conversions and activate the  
output mode of the converter (see Figure 3).  
DIGITAL OUTPUT  
BINARY TWOS COMPLEMENT  
DESCRIPTION  
ANALOG INPUT  
±10V  
BINARY CODE  
HEX CODE  
Full-Scale Range  
SYMBOL  
DESCRIPTION  
Convert Pulse Width  
MIN TYP MAX UNITS  
Least Significant  
Bit (LSB)  
305µV  
t1  
t2  
40  
7000  
8
ns  
Data Valid Delay after R/C LOW  
µs  
+Full Scale  
9.999695V  
0111 1111 1111 1111  
7FFF  
(10V 1LSB)  
t3  
t4  
BUSY Delay from R/C LOW  
BUSY LOW  
65  
8
ns  
µs  
Mid-scale  
0V  
0000 0000 0000 0000  
1111 1111 1111 1111  
0000  
FFFF  
t5  
BUSY Delay after  
End of Conversion  
220  
ns  
One LSB below  
Mid-scale  
305µV  
t6  
t7  
Aperture Delay  
Conversion Time  
40  
ns  
µs  
µs  
ns  
ns  
µs  
Full Scale  
10V  
1000 0000 0000 0000  
8000  
7.6  
8
2
Table III. Ideal Input Voltages and Output Codes.  
t8  
Acquisition Time  
t9  
Bus Relinquish Time  
BUSY Delay after Data Valid  
10  
35  
83  
PARALLEL OUTPUT (After a Conversion)  
t10  
t11  
50 200  
7.4  
After conversion nis completed and the output registers  
have been updated, BUSY (pin 26) will go HIGH. Valid data  
from conversion nwill be available on D15-D0 (pins 6-13  
and 15-22). BUSY going HIGH can be used to latch the data.  
Refer to Table IV and Figures 3 to 5 for timing specifications.  
Previous Data Valid  
after R/C LOW  
t7 + t6  
t12  
Throughput Time  
R/C to CS Setup Time  
Time Between Conversions  
9
10  
83  
µs  
ns  
µs  
ns  
10  
t13  
10  
t14  
Bus Access Time  
and BYTE Delay  
10  
TABLE IV. Conversion Timing.  
BYTE LOW  
BYTE HIGH  
+5V  
6
7
23  
22  
21  
20  
19  
18  
17  
16  
15  
6
7
23  
22  
21  
20  
19  
18  
17  
16  
15  
Bit 15 (MSB)  
Bit 14  
Bit 13  
Bit 12  
Bit 11  
Bit 10  
Bit 9  
Bit 7  
Bit 6  
Bit 0 (LSB)  
Bit 1  
Bit 8  
Bit 9  
ADS7805  
ADS7805  
8
8
Bit 5  
9
9
Bit 2  
Bit 4  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
Bit 3  
Bit 3  
Bit 4  
Bit 2  
Bit 5  
Bit 1  
Bit 8  
Bit 6  
Bit 0 (LSB)  
Bit 7  
Bit 15 (MSB)  
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).  
ADS7805  
8
SBAS020D  
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