INTERNAL CLOCK
The ADS7800 has an internal clock that is factory trimmed
to achieve a typical conversion time of 2.47µs, and a
maximum conversion time over the full operating tempera-
ture range of 2.7µs. No external adjustments are required,
and with the guaranteed maximum acquisition time of
300ns, throughput performance is assured with convert
pulses as close as 3µs.
1
2
ADS7800
±5V
Input
FIGURE 5. ±5V Range Without Trims.
READING DATA
CALIBRATION PROCEDURE
After conversion is initiated, the output buffers remain in a
Hi-Z state until the following three logic conditions are
simultaneously met: R/C is HIGH, BUSY is HIGH and CS
is LOW. Upon satisfaction of these conditions, the data lines
are enabled according to the state of HBE. See Figure 9 and
Table III for timing relationships and specifications.
First, trim offset, by applying at the input (pin 1 or 2) the
mid-point transition voltage (–2.44mV for the ±10V range,
–1.22mV for the ±5V range.) With the ADS7800 converting
continually, adjust potentiometer R1 until the MSB (D11 on
pin 5) is toggling alternately HIGH and LOW.
Next adjust full scale, by applying at the input a DC input
signal that is 3/2LSB below the nominal full scale voltage
(+9.9927V for the ±10V range, +4.9963V for the ±5V
range.) With the ADS7800 converting continually, adjust
R2 until the LSB (D0 on pin 17) is toggling HIGH and LOW
with all of the other bits HIGH.
CALIBRATION
OPTIONAL EXTERNAL GAIN AND OFFSET TRIM
Offset and full-scale errors may be trimmed to zero using
external offset and full-scale trim potentiometers connected
to the ADS7800 as shown in Figures 10 and 11.
LAYOUT CONSIDERATIONS
Because of the high resolution and linearity of the ADS7800,
system design problems such as ground path resistance and
contact resistance become very important.
If adjustment of offset and full scale is not required,
connections as shown in Figures 4 and 5 should be used.
ANALOG SIGNAL SOURCE IMPEDANCE
The input resistance of the ADS7800 is 6.3kΩ or 4.2kΩ (for
the ±10V and ±5V ranges respectively.) To avoid introduc-
ing distortion, the source resistance must be very low, or
constant with signal level. The output impedance provided
by most op amps is ideal.
±10V
1
Input
ADS7800
2
Pins 23 (VSD ) and 24 (VSA ) are not connected internally
on the ADS7800, to maximize accuracy on the chip. They
should be connected together as close as possible to the unit.
FIGURE 4. ±10V Range Without Trims.
tW
R/C
tB
BUSY
tDBC
tAP
tDBE
Converter
Acquire
Convert
tC
Acquire
tA
Convert
Mode
tDB
Data Valid
tHDR and tHL
Hi-Z State
Data
BUS
Data Valid
Hi-Z State
FIGURE 6. Convert Mode: R/C Pulse LOW — Outputs Enabled After Conversion.
®
9
ADS7800
BB [ BURR-BROWN CORPORATION ]
