ꢌ ꢒꢊ ꢗꢗ ꢁꢘ
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SBAS308A − MAY 2004 − REVISED MARCH 2005
RESET TIMING CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless
otherwise noted.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Delay from power−on of AVDD and DRVDD to
RESET pulse active
Power-on delay, t1
10
ms
Reset pulse width, t2
Pulse width of active RESET signal
2
2
µs
µs
Register write delay, t3
Delay from RESET disable to SEN active
Power Supply
(AV , DRV
)
DD DD
t ≥ 10ms
1
t ≥ 2µs
t ≥ 2µs
SEN Active
2
3
RESET (Pin 35)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D
D
D
Data is loaded at every 16th SCLK falling edge
while SEN is low.
In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D
D
Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
Minimum width of data stream for a valid loading is
16 clocks.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
7
BB [ BURR-BROWN CORPORATION ]
