ADS5510
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SLAS499–JANUARY 2007
N + 3
N + 4
N + 2
Sample
N
Analog
Input
N + 1
N + 17
N + 16
N + 14
N + 15
Signal
t
A
Input Clock
t
START
t
PDI
Output Clock
t
su
Data Out
(D0−D10)
N − 17
N − 16
N − 15
N − 14
N − 13
N − 3
N − 2
N − 1
N
Data Invalid
t
t
END
h
17.5 Clock Cycles
A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
RESET TIMING CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
=
DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted
PARAMETER
Switching Specification
DESCRIPTION
MIN
TYP
MAX
UNIT
t1
Power-on delay
Delay from power-on of AVDD and
DRVDD to RESET pulse active
10
ms
t2
t3
Reset pulse width
Pulse width of active RESET signal
2
2
µs
µs
Register write delay
Delay from RESET disable to SEN
active
Delay from power-up of AVDD and
DRVDD to output stable
Power-up time
40
ms
Power Supply
(AV , DRV
)
DD
DD
t . 10 ms
1
t . 2 ms
2
t . 2 ms
3
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
7
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