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SBAS344C–AUGUST 2005–REVISED OCTOBER 2006
CLK
DRDY
t11
SYNC
t9
t10
Valid Data
DOUT[15:0]
Figure 3. Reset Timing
Timing Specifications(1)
DESCRIPTION
MIN TYP MAX
16.667
UNIT
ns
t1
CLK period (1/fCLK)
1/t1 fCLK
1
60
MHz
ns
t2
t3
t4
t5
t6
t7
t8
t9
CLK pulse width, high or low
45%
55%
CLK to DRDY high (propagation delay)
DRDY pulse width, high or low
Previous data valid (hold time)
New data valid (setup time)
12
ns
3 t1
ns
0
ns
5
ns
RD and/or CS inactive (high) to DOUT high impedance
RD and/or CS active (low) to DOUT active
15
15
12
ns
ns
Delay from SYNC active (low) to all-zero DOUT[15:0]
ns
t10 Delay from SYNC inactive (high) to non-zero DOUT[15:0]
21 DRDY
DRDY
t11 Delay from SYNC inactive (high )to valid DOUT[15:0] (time – 55 DRDY cycles; required for digital
filter to settle).
55
(1) Output load = 10pF|| 500kΩ.
7
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