ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
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SBAS274E − MARCH 2003 − REVISED JUNE 2004
CLK
t11
t9
RESET
DRDY
t12
t10
t3
Settled
Data
DOUT[15:0]
NOTE: CS and RD tied low.
Figure 3. Reset TIming (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 3
SYMBOL
DESCRIPTION
MIN
50
TYP
MAX
UNIT
ns
t
3
10
Rising edge of CLK to DRDY low
t
9
ns
RESET pulse width
t
9
ns
Delay from RESET active (low) to DRDY forced high and DOUT forced low
RESET rising edge to falling edge of CLK
10
t
−5
10
ns
11
DRDY
Cycles
t
12
47
Delay from DOUT active to valid DOUT (settling to 0.001%)
NOTE: DOUT[15:0] and DRDY load = 10pF.
9
BB [ BURR-BROWN CORPORATION ]
