tCYC
CS/SHDN
DCLOCK
POWER
DOWN
tSUCS
tCSD
NULL
BIT
NULL
BIT
HI-Z
HI-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
B11 B10 B9 B8
DOUT
(MSB)
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
DOUT
tSUCS
POWER DOWN
tCSD
NULL
HI-Z
HI-Z
BIT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(2)
(MSB)
tSMPL
tCONV
tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS1286 Operating Sequence.
leaving the DCLOCK running to clock out the LSB first
data or zeroes. If the CS input is not running rail-to-rail, the
input logic buffer will draw current. This current may be
large compared to the typical supply current. To obtain the
lowest supply current, bring the CS pin to ground when it is
low and to supply voltage when it is high.
SERIAL INTERFACE
The ADS1286 communicates with microprocessors and other
external digital systems via a synchronous 3-wire serial inter-
face. DCLOCK synchronizes the data transfer with each bit
being transmitted on the falling DCLOCK edge and captured
on the rising DCLOCK edge in the receiving system. A falling
CS initiates data transfer as shown in Figure 1. After CS falls,
the second DCLOCK pulse enables DOUT. After one null bit,
the A/D conversion result is output on the DOUT line. Bringing
CS high resets the ADS1286 for the next data exchange.
1000
TA = 25°C
V
CC = 5V
VREF = 5V
CLK = 16 • fSAMPLE
100
10
1
f
MICROPOWER OPERATION
With typical operating currents of 250µA and automatic
shutdown between conversions, the ADS1286 achieves ex-
tremely low power consumption over a wide range of
sample rates (see Figure 2). The auto-shutdown allows the
supply current to drop with sample rate.
0.1k
1k
10k
100k
SHUTDOWN
Sample Rate (kHz)
The ADS1286 is equipped with automatic shutdown fea-
tures. The device draws power when the CS pin is LOW and
shuts down completely when the pin is HIGH. The bias
circuit and comparator powers down and the reference input
becomes high impedance at the end of each conversion
FIGURE 2. Automatic Power Shutdown Between Conver-
sions Allows Power Consumption to Drop with
Sample Rate.
®
9
ADS1286
BB [ BURR-BROWN CORPORATION ]
