SPECIFICATIONS
At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, , fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS1286, ADS1286A
ADS1286K, ADS1286B
ADS1286C, ADS1286L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Range
Absolute Input Voltage
+In – (–In)
+In
0
–0.2
–0.2
VREF
VCC +0.2
+0.2
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
–In
Capacitance
Leakage Current
25
±1
✻
✻
✻
✻
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity
Differential Linearity
Offset Error
Gain Error
Noise
Power Supply Rejection
12
✻
✻
Bits
Bits
12
✻
✻
±1
±0.5
0.75
±2
50
82
±2
±1.0
±3
✻
✻
✻
✻
✻
✻
✻
±0.75
✻
±0.5
±0.25
✻
✻
✻
±1
±0.75
✻
LSB
LSB
LSB
LSB
µVrms
dB
±8
✻
✻
✻
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
12
✻
✻
Clk Cycles
Clk Cycles
kHz
1.5
✻
✻
Small Signal Bandwidth
500
✻
✻
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
V
V
V
V
IN = 5.0Vp-p at 1kHz
IN = 5.0Vp-p at 5kHz
IN = 5.0Vp-p at 1kHz
IN = 5.0Vp-p at 1kHz
–85
–83
72
✻
✻
✻
✻
✻
✻
✻
✻
dB
dB
dB
dB
SINAD
Spurious Free Dynamic Range
90
REFERENCE INPUT
REF Input Range
Input Resistance
1.25
2.5
5000
5000
0.01
2.4
VCC+0.05V
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
CS = VCC
CS = GND, fCLK = 0Hz
CS = VCC
tCYC ≥ 640µs, fCLK ≤ 25kHz
tCYC = 80µs, fCLK = 200kHz
MΩ
MΩ
µA
µA
µA
Current Drain
2.5
20
20
✻
✻
✻
✻
✻
✻
2.4
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
CMOS
✻
✻
IIH = +5µA
IIL = +5µA
IOH = 250µA
IOL = 250µA
3
0.0
3
+VCC
0.8
+VCC
0.4
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
VOL
0.0
Data Format
Straight Binary
✻
✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
VCC
+4.50
5
200
250
5.25
400
500
3
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
Quiescent Current, VANA
tCYC ≥ 640µS, fCLK ≤ 25kHz
µA
µA
µA
tCYC = 90µS, fCLK = 200kHz
Power Down
CS = VCC
TEMPERATURE RANGE
Specified Performance
ADS1286, K, L
ADS1286A, B, C
0
–40
+70
+85
✻
✻
✻
✻
✻
✻
✻
✻
°C
°C
✻ Specifications same as grade to the left.
TIMING CHARACTERISTICS
fCLK = 200kHz, TA = TMIN to TMAX
.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSMPL
tSMPL (MAX)
tCONV
tdDO
tdis
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
ADS1286
1.5
2.0
20
Clk Cycles
kHz
See Operating Sequence
See Test Circuits
12
85
25
50
30
70
60
Clk Cycles
Delay TIme, DCLOCK↓ to DOUT Data Valid
Delay TIme, CS↑ to DOUT Hi-Z
Delay TIme, DCLOCK↓ to DOUT Enable
Output Data Remains Valid After DCLOCK↓
DOUT Fall Time
150
50
ns
ns
ns
ns
ns
ns
ns
ns
See Test Circuits
ten
See Test Circuits
100
thDO
tf
CLOAD = 100pF
15
30
See Test Circuits
100
100
0
tr
DOUT Rise Time
See Test Circuits
tCSD
tSUCS
Delay Time, CS↓ to DCLOCK↓
Delay Time, CS↓ to DCLOCK↑
See Operating Sequence
See Operating Sequence
®
ADS1286
2
BB [ BURR-BROWN CORPORATION ]
