ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
tCPW
tCLK
CLK
tCPW
tCS
tFRAME
tFPW
tFPW
FSYNC
SCLK
DOUT
DIN
tFS
tSCLK
tSPW
tSF
tSPW
tMSBPD
Bit 23 (MSB)
tDOPD
tDOHD
Bit 21
Bit 22
tDIST
tDIHD
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL PARAMETER
MIN
37
TYP
MAX
UNIT
ns
All modes
10,000
tCLK
CLK period (1/fCLK)
High-Speed mode only
30.5
12
ns
tCPW
tCS
CLK positive or negative pulse width
ns
Falling edge of CLK to falling edge of SCLK
–0.25
256
1
0.25
tCLK
tCLK
tSCLK
ns
(1)
tFRAME
tFPW
tFS
Frame period (1/fDATA
)
2560
FSYNC positive or negative pulse width
Rising edge of FSYNC to rising edge of SCLK
Rising edge of SCLK to rising edge of FSYNC
SCLK period(2)
5
tSF
5
ns
tSCLK
tSPW
1
tCLK
tCLK
ns
SCLK positive or negative pulse width
0.4
10
(3)(4)
tDOHD
SCLK falling edge to old DOUT invalid (hold time)
SCLK falling edge to new DOUT valid (propagation delay)
FSYNC rising edge to DOUT MSB valid (propagation delay)
New DIN valid to falling edge of SCLK (setup time)
Old DIN valid to falling edge of SCLK (hold time)
(4)
tDOPD
tMSBPD
tDIST
31
31
ns
ns
6
6
ns
(3)
tDIHD
ns
(1) Depends on MODE[1:0] and CLKDIV selection. See Table 6 (fCLK/fDATA).
(2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK
.
(3) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.
(4) Load on DOUT = 20pF.
9
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS1274 ADS1278
BB [ BURR-BROWN CORPORATION ]
