ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Inputs
Full-scale input voltage (FSR(1)
Absolute input voltage
)
VIN = (AINP – AINN)
AINP or AINN to AGND
VCM = (AINP + AINN)/2
±VREF
V
V
AGND – 0.1
AVDD + 0.1
Common-mode input voltage (VCM
)
2.5
14
V
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
kΩ
kΩ
kΩ
kΩ
14
Differential input impedance
28
140
DC Performance
Resolution
No missing codes
fCLK = 32.768MHz(2)
fCLK = 27MHz
24
Bits
SPS
SPS(3)
128,000
105,469
52,734
52,734
10,547
±0.0003
0.25
High-Speed mode
Data rate (fDATA
)
High-Resolution mode
Low-Power mode
Low-Speed mode
SPS
SPS
SPS
% FSR(1)
Integral nonlinearity (INL)(4)
Offset error
Differential input, VCM = 2.5V
±0.0012
2
mV
Offset drift
0.8
μV/°C
% FSR
ppm/°C
μV, rms
μV, rms
μV, rms
μV, rms
dB
Gain error
0.1
0.5
Gain drift
1.3
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
Shorted input
Shorted input
Shorted input
Shorted input
fCM = 60Hz
8.5
16
12
16
16
5.5
Noise
8.5
8.0
Common-mode rejection
Power-supply rejection
VCOM output voltage
90
108
AVDD
DVDD
IOVDD
80
dB
fPS = 60Hz
No load
85
dB
105
dB
AVDD/2
V
(1) FSR = full-scale range = 2VREF
.
(2) fCLK = 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When fCLK > 27MHz, operation is limited to
Frame-Sync mode and VREF ≤ 2.6V.
(3) SPS = samples per second.
(4) Best fit method.
3
Copyright © 2007, Texas Instruments Incorporated
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