ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
ADS1274/ADS1278 PIN DESCRIPTIONS (continued)
PIN
NAME
AINN1
AINN2
AINN3
AINN4
AINN5
AINN6
AINN7
AINN8
AVDD
VCOM
VREFN
VREFP
CLK
NO.
FUNCTION
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
DESCRIPTION
4
2
64
ADS1278:
ADS1274:
AINN[8:1] Negative analog input, channels 8 through 1.
62
52
AINN[8:5] Connected to internal ESD rails. The inputs may float.
AINN[4:1] Negative analog input, channels 4 through 1.
50
48
46
5, 44, 53, 60
Analog power supply Analog power supply (4.75V to 5.25V).
55
57
56
27
Analog output
Analog input
Analog input
Digital input
AVDD/2 Unbuffered voltage output.
Negative reference input.
Positive reference input.
Master clock input.
CLK input divider control:
1 = 32.768MHz (High-Speed mode only) / 27MHz
0 = 13.5MHz (low-power) / 5.4MHz (low-speed)
CLKDIV
10
Digital input
DGND
DIN
7, 21, 24, 25
Digital ground
Digital input
Digital ground power supply.
Daisy-chain data input.
12
20
19
18
17
16
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
Digital output
Digital output
Digital output
Digital output
Digital output
DOUT1 is TDM data output (TDM mode).
ADS1278:
ADS1274:
DOUT[8:1] Data output for channels 8 through 1.
DOUT[8:5] Internally connected to active circuitry; outputs are
driven.
DOUT6
15
Digital output
DOUT[4:1] Data output for channels 4 through 1.
DOUT7
DOUT8
14
13
Digital output
Digital output
DRDY/
FSYNC
29
Digital input/output
Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
DVDD
FORMAT0
FORMAT1
FORMAT2
IOVDD
26
32
31
30
22, 23
34
33
42
41
40
39
38
37
36
35
28
11
8
Digital power supply Digital core power supply (+1.65V to +1.95V).
Digital input
FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs,
fixed/dynamic position TDM data, and modulator mode/normal operating mode.
Digital input
Digital input
Digital power supply I/O power supply (+1.65V to +3.6V).
MODE0
MODE1
PWDN1
PWDN2
PWDN3
PWDN4
PWDN5
PWDN6
PWDN7
PWDN8
SCLK
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input/output
Digital input
Digital input
MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed
mode operation.
ADS1278:
ADS1274:
PWDN[8:1] Power-down control for channels 8 through 1.
PWDN[8:5] must = 0V.
PWDN[4:1] Power-down control for channels 4 through 1.
Serial clock input, Modulator clock output.
Synchronize input (all channels).
SYNC
TEST0
TEST[1:0] Test mode select: 00 = Normal operation
01 = Do not use
10 = Do not use
11 = Boundary scan test
mode
TEST1
9
Digital input
7
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