ꢇ ꢍꢚ ꢛꢀ ꢀꢀ
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SBAS314A − APRIL 2004 − REVISED SEPTEMBER 2004
Analog Input Measurement without the Input Buffer
With the buffer disabled by setting the BUFEN pin low,
the ADS1222 measures the input signal using internal
capacitors that are continuously charged and
discharged. Figure 14 shows a simplified schematic of
the ADS1222 input circuitry, with Figure 15 showing the
VDD/2
(1)
Ω
Ω
ZeffA = tSAMPLE/CA1 = 6M
AINPx
AINNx
(1)
Ω
ZeffB = tSAMPLE/CB = 3M
on/off timings of the switches. The S switches close
1
during the input sampling phase. With S1 closed, C
A1
(1)
ZeffA = tSAMPLE/CA2 = 6M
charges to AINP, C charges to AINN, and C charges
A2
B
to (AINP – AINN). For the discharge phase, S opens
VDD/2
NOTE: (1) fCLK = 2MHz.
1
first and then S closes. C
and C
discharge to
2
A1
A2
approximately VDD/2 and C discharges to 0V. This
B
two-phase sample/discharge cycle repeats with a
Figure 16. Effective Analog Input Impedances
with the Buffer Off
frequency of f
/32 (62.5kHz for f
= 2MHz).
CLK
CLK
ESD diodes protect the inputs. To keep these diodes
from turning on, make sure the voltages on the input
pins do not go below GND by more than 100mV, and
likewise do not exceed VDD by 100mV:
ESD Protection
VDD
VDD/2
CA1
3pF
S2
S1
S1
GND – 100mV < (AINP, AINN) < VDD + 100mV
AINP
AINN
AINPx
AINNx
Analog Input Measurement with the Input Buffer
When the buffer is enabled by setting the BUFEN pin
high, a low-drift, chopper-stabilized input buffer is used
to achieve very high input impedance. The buffer
charges the input sampling capacitors, thus removing
the load from the measurement. Because the input
buffer is chopper-stabilized, the charging of parasitic
capacitances causes the charge to be carried away, as
if by resistance. The input impedance can be modeled
by a single resistor, as shown in Figure 17. The
CB
6pF
Mux
S2
CA2
3pF
VDD
VDD/2
Figure 14. Simplified Input Structure with the
Buffer Turned Off
impedance scales inversely with f
the nonbuffered case.
frequency, as in
CLK
tSAMPLE = 32/fCLK
ON
S1
OFF
ON
AINP
(1)
Ω
1.2G
S2
OFF
AINN
NOTE: (1) fCLK = 2MHz.
Figure 15. S and S Switch Timing for Figure 14
1
2
The constant charging of the input capacitors presents
a load on the inputs that can be represented by effective
impedances. Figure 16 shows the input circuitry with
the capacitors and switches of Figure 14 replaced by
their effective impedances. These impedances scale
Figure 17. Effective Analog Input Impedances
with the Buffer On
Note that the analog inputs (listed in the Electrical
Characteristics table as Absolute Input Range) must
remain between GND + 0.05V to VDD − 1.5V.
Exceeding this range degrades linearity and results in
performance outside the specified limits.
inversely with f
frequency. For example, if f
CLK
CLK
frequency is reduced by a factor of 2, the impedances
will double.
9
BB [ BURR-BROWN CORPORATION ]
