ADS1211 SIMPLIFIED BLOCK DIAGRAM
AGND AVDD
REFOUT
20
REFIN
21
VBIAS
7
XIN
10
XOUT
11
6
19
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
12 DGND
13 DVDD
4
AIN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
5
A
Micro Controller
2
A
Second-Order
∆∑
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
3
Third-Order
Digital Filter
A
MUX
PGA
24
1
A
A
Full-Scale Register
22
23
A
14
A
SCLK
15
Modulator Control
Serial Interface
SDIO
16
SDOUT
9
8
18
17
DSYNC
CS
MODE DRDY
ADS1211P AND ADS1211U PIN CONFIGURATION
ADS1211P AND ADS1211U PIN DEFINITIONS
PIN NO
NAME
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
DESCRIPTION
TOP VIEW
DIP/SOIC
1
2
Inverting Input Channel 3.
Noninverting Input Channel 2.
Inverting Input Channel 2.
Noninverting Input Channel 1.
Inverting Input Channel 1.
Analog Ground.
3
4
A
IN3N
AIN2P
IN2N
IN1P
IN1N
1
2
3
4
5
6
7
8
9
24 AIN3P
23 AIN4N
5
6
7
Bias Voltage Output, +3.3V nominal.
Chip Select Input.
A
22
AIN4P
8
CS
A
21 REFIN
20 REFOUT
19 AVDD
9
DSYNC
XIN
Control Input to Synchronize Serial Output Data.
System Clock Input.
10
11
12
13
14
15
A
XOUT
System Clock Output (for Crystal or Resonator).
Digital Ground.
DGND
DVDD
SCLK
SDIO
AGND
VBIAS
Digital Supply, +5V nominal.
ADS1211P
ADS1211U
18 MODE
17 DRDY
16 SDOUT
15 SDIO
14 SCLK
13 DVDD
Clock Input/Output for serial data transfer.
Serial Data Input (can also function as Serial Data
Output).
CS
16
17
18
19
20
21
22
23
24
SDOUT
DRDY
MODE
AVDD
Serial Data Output.
DSYNC
Data Ready.
XIN 10
XOUT 11
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output: +2.5V nominal.
Reference Input.
REFOUT
REFIN
AIN4P
DGND 12
Noninverting Input Channel 4.
Inverting Input Channel 4.
Noninverting Input Channel 3.
AIN4N
AIN3P
®
5
ADS1210, 1211
BB [ BURR-BROWN CORPORATION ]
