ꢙ ꢚꢉ ꢛꢜ ꢝꢞ
ꢙ ꢚꢉ ꢛꢜ ꢝꢟ
www.ti.com
SBAS311 − MARCH 2004
PIN ASSIGNMENTS
Terminal Functions
TERMINAL
NAME
VSSOP PACKAGE
(TOP VIEW)
NO.
DESCRIPTION
1
2
3
4
5
6
7
8
CLKOUT
CLKIN
Clock output
Master clock input
Ground
BUF
FOUT
VDD
CLKOUT
CLKIN
1
2
3
4
8
7
6
5
GND
REFIN/OUT
VIN
Reference voltage input or output
Analog input
GND
V
DD
Power supply, +3.3V or +5V nominal
Modulator output
VIN
REFIN/OUT
FOUT
BUF
Buffered mode select
PARAMETER MEASUREMENT INFORMATION
tC1
CLKIN
tW1
tD1
FOUT
tW2
tR1
tF1
Figure 1. Timing Diagram
TIMING REQUIREMENTS: 5.0V
over recommended operating free-air temperature range at −40°C to +85°C,, and V
DD
= 5V, unless otherwise noted.
PARAMETER
MIN
1000
250
MAX
TBD
TBD
UNITS
ns
ADS1206
ADS1207
t
Input clock period
C1
ns
t
t
t
t
t
Input clock high time
(t /2) − 100
C1
(t /2) + 100
C1
ns
W1
D1
W2
R1
F1
FOUT rising edge delay after input clock rising edge
FOUT high time
TBD
TBD
ns
t
− 20
TBD
TBD
t
+ 20
TBD
TBD
ns
C1
C1
FOUT rise time
ns
FOUT fall time
ns
:
NOTE Applicablefor 5.0V nominal supply: V
(min) = 4.5V and V (max) = 5.5V. All input signals are specified with t = t = 5ns (10% to 90%
DD R F
DD
of V ) and timed from a voltage level of (V + V )/2. See timing diagram.
DD
IL
IH
TIMING REQUIREMENTS: 3.3V
over recommended operating free-air temperature range at −40°C to +85°C,, and V
= 3.3V, unless otherwise noted.
DD
PARAMETER
MIN
1000
250
MAX
TBD
TBD
UNITS
ns
ADS1206
t
Input clock period
C1
ADS1207
ns
t
t
t
t
t
Input clock high time
(t /2) − 100
C1
(t /2) + 100
C1
ns
W1
D1
W2
R1
F1
FOUT rising edge delay after input clock rising edge
FOUT high time
TBD
TBD
ns
t
− 8
t
+ 8
ns
C1
C1
FOUT rise time
TBD
TBD
TBD
ns
FOUT fall time
TBD
ns
:
NOTE Applicablefor 3.3V nominal supply: V
DD
(min) = 3.0V and V (max) = 3.6V. All input signals are specified with t = t = 5ns (10% to 90%
DD R F
of V ) and timed from a voltage level of (V + V )/2. See timing diagram.
DD IL IH
5
BB [ BURR-BROWN CORPORATION ]
