TIMING DIAGRAMS (Cont.)
tC4
MCLK
MDAT
tw4
tD4
DIAGRAM 4: Mode 3 Operation.
TIMING CHARACTERISTICS
over recommended operating free-air temperature range –40°C to +85°C, VDD = 5V, and MCLK = 10MHz, unless otherwise noted.
SPEC
DESCRIPTION
MODE
MIN
MAX
UNITS
tC1
tW1
tD1
tC2
tW2
tD2
tD3
tC3
tW3
tC4
tW4
tD4
tR1
tF1
Clock Period
0
0
0
1
1
1
1
2
2
3
3
3
3
3
90
tC1/2 – 5
tC1/4 – 10
180
110
tC1/2 + 5
tC1/4 + 10
220
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock HIGH Time
Data delay after rising edge of clock
Clock Period
Clock HIGH Time
tC2/2 – 5
tC2/4 – 10
tC2/4 – 10
90
tC2/2 + 5
tC2/4 + 10
tC2/4 + 10
110
Data delay after rising edge of clock
Data delay after falling edge of clock
Clock Period
Clock HIGH Time
tC3/2 – 5
45
tC3/2 + 5
55
Clock Period
Clock HIGH Time
10
tC4 – 10
10
Data delay after falling edge of clock
Rise Time of Clock
0
0
10
Fall Time of Clock
0
10
NOTE: All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams 1 thru 4.
ADS1202
5
SBAS275
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