An input differential signal of 0V will ideally produce a
stream of ones and zeros that are HIGH 50% of the time and
LOW 50% of the time. A differential input of 5V will
produce a stream of ones and zeros that are HIGH 90% of
the time. A differential input of –5V will produce a stream
of ones and zeros that are HIGH 10% of the time. The input
voltage versus the output modulator signal is shown in
Figure 8.
BIASEN
VBIAS
LOW
High Impedance
1.33V • VREF
HIGH
TABLE II. Bias Enable.
When enabled, the VBIAS circuitry consumes approximately
1mA with no external load. The maximum current into or
out of VBIAS should not exceed 10mA.
OFFSET and GAIN CALIBRATION
On power-up, external signals may be present before VBIAS
is enabled. This can create a situation in which a negative
voltage is applied to the analog inputs, reverse biasing the
negative input protection diode of the ADS1201. This situ-
ation should not be a problem as long as the resistors R1 and
R2 limit the current being sourced by each analog input to be
under 10mA. A potential of 0V at the analog input pin (AINP
or AINN) should be used in the calculation.
The ADS1201 offers a self-calibration function that is imple-
mented with the GAIN/OFFSET and CALEN pins. Both
conditions provide an output stream of data, similar to
normal operation where the converter is configured to sample
an input signal at AIN.
The offset and gain errors of the ADS1201 are calibrated
independently. For best operation, the offset should be
calibrated first, followed by the gain. The calibration imple-
mentation timing diagram is shown in Figure 9. The calibra-
tion mode pins control the calibration functions of the
ADS1201.
DIGITAL OUTPUT
The timing diagram for the ADS1201 data retrieval is shown
in Figure 7. MCLK initiates the modulator process for the
ADS1201 and is used as a system clock by the ADS1201, as
well as a framing clock for data out. The modulator output
data, which is a serial stream, is available on the MOUT pin.
Typically, MOUT is read on the falling edge of MCLK.
Under any situation with MCLK, the duty cycle must be
kept constant for reliable, repeatable results.
Calibration should be performed once and then normal
operation can be resumed. Calibration of offset and gain is
recommended immediately after power-on and whenever
there is a “significant” change in the operating environment.
Significant changes in the operating environment include a
change of the MCLK frequency, MCLK duty cycle, power
Modulator Output
+FS (Analog Input)
–FS (Analog Input)
Analog Input
FIGURE 8. Analog Input versus Modulator Output of the ADS1201.
t9
t8
CAL
SYMBOL
DESCRIPTION
MIN
TYP
10
MAX
UNITS
ns
t
CAL and GAIN/OFFSET Rise Time
CAL and GAIN/OFFSET Fall Time
GAIN/OFFSET to CAL Setup Time
GAIN/OFFSET to CAL Hold Time
8
t
10
ns
9
t8
t9
t
0
ns
t10
10
GAIN/OFFSET
(1)
t
2.5 TMCLK
ns
11
t11
NOTE: (1) TMCLK is the clock period of MCLK.
FIGURE 9. Timing Diagram for the Calibration Feature of the ADS1201.
®
9
ADS1201
BB [ BURR-BROWN CORPORATION ]
