CONVERSION START
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely termi-
nated or restarted. However, if AO changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of AO, possibly resulting
in an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
The converter is commanded to initiate a conversion by a
transition occurring on any of three logic inputs (CE, CS,
and R/C) as shown in Table II. Conversion is initiated by the
last of the three to reach the required state and thus all three
may be dynamically controlled. If necessary, all three may
change state simultaneously, and the nominal delay time is
the same regardless of which input actually starts conver-
sion. If it is desired that a particular input establish the actual
start of conversion, the other two should be stable a mini-
mum of 50ns prior to the transition of that input. Timing
relationships for start of conversion timing are illustrated in
Figure 3. The specifications for timing are contained in
Table IV.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and AO. See Figure 4 and Table IV for timing relation-
The STATUS output indicates the current state of the con-
verter by being in a high state only during conversion.
During this time the three-state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
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ADC774
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BB [ BURR-BROWN CORPORATION ]
