TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15V unless otherwise noted.
POWER SUPPLY REJECTION vs
SUPPLY RIPPLE FREQUENCY
GAIN DRIFT ERROR (% OF FSR)
vs TEMPERATURE
+0.08
0.1
0.06
0.04
–15VDC
+0.04
0
0.02
0.01
+15VDC
–0.04
–0.08
–0.12
0.006
0.004
NOTE: Pa g es
+5VDC
10k
0.002
4 &5 w ere
0.001
1
10
100
1k
100k
+85
–25
+25
sw it ch ed fo r
Frequency (Hz)
Temperature (°C)
a b rid g e versio n
THEORY OF OPERATION
fo r '9 6 d a t a b o o k.
The accuracy of a successive approximation A/D converter
is described by the transfer function shown in Figure 1. All
successive approximation A/D converters have an inherent
quantization error of ±1/2LSB. The remaining errors in the
A/D converter are combinations of analog errors due to the
linear circuitry, matching and tracking properties of the
ladder and scaling networks, power supply rejection, and
reference errors. In summary, these errors consist of initial
errors including Gain, Offset, Linearity, Differential Linear-
ity, and Power Supply Sensitivity. Initial Gain and Offset
errors may be adjusted to zero. Gain drift over temperature
rotates the line (Figure l) about the zero or minus full scale
point (all bits Off) and Offset drift shifts the line left or right
over the operating temperature range. Linearity error is
unadjustable and is the most meaningful indicator of A/D
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at any
level over the range of the A/D converter. A differential
linearity error of ±1/2LSB means that the width of each bit
step over the range of the A/D converter is 1LSB, ±1/2LSB.
The ADC76 is also monotonic, assuring that the output
Be su re t o sw it ch
digital code either increases or remains the same for increas-
ing analog input signals. Burr-Brown also guarantees that
this cbonvaercterkwilfl hoavre nofumislslingPcoDdesSo.ver a specified
temperature range when short cycled for 14-bit operation
TIMING CONSIDERATIONS
The timing diagram in Figure 2 assumes an analog input
such that the positive true digital word 1001 1000 1001 0110
exists. The output will be complementary as shown in Figure
2 (0110 0111 0110 1001 is the digital output). Figures 3 and
4 are timing diagrams showing the relationship of serial data
to clock, and valid data to status.
DIGITAL CODES
Parallel Data
Two binary codes are available on the ADC76 parallel
output: they are complementary (logic “0” is true) straight
binary (CSB) for unipolar input signal ranges, and comple-
mentary offset binary (COB) for bipolar input signal ranges.
Complementary two’s complement (CTC) may be obtained
by inverting the MSB (pin 1).
All Bit On
0000 ... 0000
Gain
Error
0000 ... 0001
0011 ... 1100
0011 ... 1110
0111 ... 1111
1000 ... 0000
1000 ... 0001
1111 ... 1110
1111 ... 1111
Table I shows the LSB, transition values, and code defini-
tions for each possible analog input signal range for 12-, 13-
and 14-bit resolutions. Figure 5 shows the connections for
14-bit resolution, parallel data output, with ±10V input.
–1/2LSB
+1/2LSB
Offset
Error
Serial Data
eIN On
All Bits Off
Two straight binary (complementary) codes are available on
the serial output line: CSB and COB. The serial data is
available only during conversion and appears with MSB
occurring first. The serial data is synchronous with the
internal clock as shown in the timing diagrams of Figures 2
and 3. The LSB and transition values shown in Table I also
apply to the serial data output except for the CTC code.
Analog Input
+FSR/2–1LSB
–FSR/2
eIN Off
*See Table I for Digital Code Definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar A/D
Converter.
®
5
ADC76
BB [ BURR-BROWN CORPORATION ]
