LAYOUT AND
OPERATING INSTRUCTIONS
LAYOUT PRECAUTIONS
Direct
Input
22
25
24
R2
5kΩ
R1
5kΩ
Comp
In
Analog and digital common are not connected internally in
the ADC76, but should be connected together as close to the
unit as possible, preferably to a large plane under the ADC.
If these grounds must be run separately, use a wide conduc-
tor pattern and a 0.01µF to 0.1µF nonpolarized bypass
capacitor between analog and digital commons at the unit.
Low impedance analog and digital common returns are
essential for low noise performance. Coupling between
analog inputs and digital lines should be minimized by
careful layout. The comparator input (pin 27) is extremely
sensitive to noise. Any connection to this point should be as
short as possible and shielded by Analog Common or
±15VDC supply patterns.
27
26
6.3kΩ
From D/A
Converter
Comparator
to Logic
VREF
Bipolar
Offset
FIGURE 8. ADC76 Input Scaling Circuit.
OUTPUT DRIVE
Normally all ADC76 logic outputs will drive two standard
TTL loads; however, if long digital lines must be driven,
external logic buffers are recommended.
INPUT IMPEDANCE
POWER SUPPLY DECOUPLING
The input signal to the ADC76 should be low impedance,
such as the output of an op amp, to avoid any errors due to
the relatively low input impedance of the ADC76.
The power supplies should be bypassed with tantalum or
electrolytic capacitors as shown in Figure 7 to obtain noise
free operation. These capacitors should be located close to
the ADC.
If this impedance is not low, a buffer amplifier should be
added between the input signal and the direct input to the
ADC76 as shown in Figure 9.
21
–15VDC
30
+5VDC
1µF
Analog
Common
+
+
Connect to
Pin 24 or Pin 25
Analog
Input Signal
22
28
+
–
+
1µF
19
OPA633
1µF
10MΩ
Digital
Common
To Star (Meeting Point) Ground
+15VDC
FIGURE 7. Recommended Power Supply Decoupling.
FIGURE 9. Source Impedance Buffering.
OPTIONAL EXTERNAL GAIN
AND OFFSET ADJUSTMENTS
INPUT SCALING
The analog input should be scaled as close to the maximum
input signal range as possible in order to utilize the maxi-
mum signal resolution of the A/ D converter. Connect the
input signal as shown in Table II. See Figure 8 for circuit
details.
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to the
ADC as shown in Figures 10 and 11. Multiturn potentiome-
ters with 100ppm/°C or better TCRs are recommended for
minimum drift over temperature and time. These pots may
be any value from 10kΩ to 100kΩ. All resistors should be
20% carbon or better. Pin 29 (Gain Adjust) and pin 27
(Offset Adjust) may be left open if no external adjustment is
required; however, pin 29 should always be bypassed with
0.01µF to Analog Common.
CONNECT
INPUT
SIGNAL
RANGE
CONNECT
PIN 26
TO PIN
CONNECT
PIN 24
TO
INPUT
SIGNAL
TO PIN
OUTPUT
CODE
±10V
±5V
±2.5V
0 to +5V
0 to +10V
0 to +20V
COB or CTC*
COB or CTC*
COB or CTC*
CSB
27
27
27
22
22
22
Input Signal
Open
Pin 27
Pin 27
Open
24
25
25
25
25
24
CSB
CSB
ADJUSTMENT PROCEDURE
Input Signal
Offset—Connect the Offset potentiometer (make sure R1 is
as close to pin 27 as possible) as shown in Figure 10.
*Obtained by inverting MSB pin 1.
TABLE II. ADC76 Input Scaling Connections.
Sweep the input through the end point transition voltage that
should cause an output transition to all bits off (EIN Off),
Figure 1.
®
7
ADC76
BB [ BURR-BROWN CORPORATION ]
